Lines Matching refs:to

11 to a memory region with the DMA_ATTR_WRITE_BARRIER attribute forces
12 all pending DMA writes to complete, and thus provides a mechanism to
14 bridges.  This barrier is not specific to a particular type of
15 interconnect, it applies to the system as a whole, and so its
17 the way from the DMA device to memory.
20 useful, suppose that a device does a DMA write to indicate that data is
28 DMA_ATTR_WEAK_ORDERING specifies that reads and writes to the mapping
31 Since it is optional for platforms to implement DMA_ATTR_WEAK_ORDERING,
38 DMA_ATTR_WRITE_COMBINE specifies that writes to the mapping may be
39 buffered to improve performance.
41 Since it is optional for platforms to implement DMA_ATTR_WRITE_COMBINE,
48 DMA_ATTR_NON_CONSISTENT lets the platform to choose to return either
50 you are guaranteeing to the platform that you have all the correct and
56 DMA_ATTR_NO_KERNEL_MAPPING lets the platform to avoid creating a kernel
60 Buffers allocated with this attribute can be only passed to user space
63 can treat it as a cookie that must be passed to dma_mmap_attrs() and
67 Since it is optional for platforms to implement
75 buffer from CPU domain to device domain. Some advanced use cases might
79 for the given buffer with device pointer to each device taking part in
81 to 'device' domain, what synchronizes CPU caches for the given region
83 depending on the dma direction). However, next calls to
87 large, so it is highly recommended to avoid it if possible.
88 DMA_ATTR_SKIP_CPU_SYNC allows platform code to skip synchronization of
90 transferred to 'device' domain. This attribute can be also used for
91 dma_unmap_{single,page,sg} functions family to force buffer to stay in
98 By default DMA-mapping subsystem is allowed to assemble the buffer
101 specifying this attribute the allocated buffer is forced to be contiguous