Lines Matching refs:msp
120 static void set_prot_desc_tx(struct ux500_msp *msp, in set_prot_desc_tx() argument
130 if (msp->def_elem_len) { in set_prot_desc_tx()
144 writel(temp_reg, msp->registers + MSP_TCF); in set_prot_desc_tx()
147 static void set_prot_desc_rx(struct ux500_msp *msp, in set_prot_desc_rx() argument
157 if (msp->def_elem_len) { in set_prot_desc_rx()
172 writel(temp_reg, msp->registers + MSP_RCF); in set_prot_desc_rx()
175 static int configure_protocol(struct ux500_msp *msp, in configure_protocol() argument
183 msp->def_elem_len = config->def_elem_len; in configure_protocol()
186 dev_err(msp->dev, "%s: ERROR: Invalid protocol!\n", in configure_protocol()
197 dev_err(msp->dev, in configure_protocol()
204 set_prot_desc_tx(msp, protdesc, data_size); in configure_protocol()
206 set_prot_desc_rx(msp, protdesc, data_size); in configure_protocol()
209 temp_reg = readl(msp->registers + MSP_GCR) & ~TX_CLK_POL_RISING; in configure_protocol()
211 writel(temp_reg, msp->registers + MSP_GCR); in configure_protocol()
212 temp_reg = readl(msp->registers + MSP_GCR) & ~RX_CLK_POL_RISING; in configure_protocol()
214 writel(temp_reg, msp->registers + MSP_GCR); in configure_protocol()
219 static int setup_bitclk(struct ux500_msp *msp, struct ux500_msp_config *config) in setup_bitclk() argument
228 reg_val_GCR = readl(msp->registers + MSP_GCR); in setup_bitclk()
229 writel(reg_val_GCR & ~SRG_ENABLE, msp->registers + MSP_GCR); in setup_bitclk()
252 dev_err(msp->dev, "%s: ERROR: Unknown protocol (%d)!\n", in setup_bitclk()
261 writel(temp_reg, msp->registers + MSP_SRG); in setup_bitclk()
263 msp->f_bitclk = (config->f_inputclk)/(sck_div + 1); in setup_bitclk()
267 reg_val_GCR = readl(msp->registers + MSP_GCR); in setup_bitclk()
268 writel(reg_val_GCR | SRG_ENABLE, msp->registers + MSP_GCR); in setup_bitclk()
274 static int configure_multichannel(struct ux500_msp *msp, in configure_multichannel() argument
283 dev_err(msp->dev, in configure_multichannel()
297 reg_val_MCR = readl(msp->registers + MSP_MCR); in configure_multichannel()
300 msp->registers + MSP_MCR); in configure_multichannel()
302 msp->registers + MSP_TCE0); in configure_multichannel()
304 msp->registers + MSP_TCE1); in configure_multichannel()
306 msp->registers + MSP_TCE2); in configure_multichannel()
308 msp->registers + MSP_TCE3); in configure_multichannel()
310 dev_err(msp->dev, in configure_multichannel()
318 reg_val_MCR = readl(msp->registers + MSP_MCR); in configure_multichannel()
321 msp->registers + MSP_MCR); in configure_multichannel()
323 msp->registers + MSP_RCE0); in configure_multichannel()
325 msp->registers + MSP_RCE1); in configure_multichannel()
327 msp->registers + MSP_RCE2); in configure_multichannel()
329 msp->registers + MSP_RCE3); in configure_multichannel()
331 dev_err(msp->dev, in configure_multichannel()
337 reg_val_MCR = readl(msp->registers + MSP_MCR); in configure_multichannel()
340 msp->registers + MSP_MCR); in configure_multichannel()
343 msp->registers + MSP_RCM); in configure_multichannel()
345 msp->registers + MSP_RCV); in configure_multichannel()
353 static int enable_msp(struct ux500_msp *msp, struct ux500_msp_config *config) in enable_msp() argument
359 configure_protocol(msp, config); in enable_msp()
360 setup_bitclk(msp, config); in enable_msp()
362 status = configure_multichannel(msp, config); in enable_msp()
364 dev_warn(msp->dev, in enable_msp()
371 !msp->capture_dma_data.dma_cfg) { in enable_msp()
372 dev_err(msp->dev, "%s: ERROR: MSP RX-mode is not configured!", in enable_msp()
377 !msp->playback_dma_data.dma_cfg) { in enable_msp()
378 dev_err(msp->dev, "%s: ERROR: MSP TX-mode is not configured!", in enable_msp()
383 reg_val_DMACR = readl(msp->registers + MSP_DMACR); in enable_msp()
388 writel(reg_val_DMACR, msp->registers + MSP_DMACR); in enable_msp()
390 writel(config->iodelay, msp->registers + MSP_IODLY); in enable_msp()
393 reg_val_GCR = readl(msp->registers + MSP_GCR); in enable_msp()
394 writel(reg_val_GCR | FRAME_GEN_ENABLE, msp->registers + MSP_GCR); in enable_msp()
399 static void flush_fifo_rx(struct ux500_msp *msp) in flush_fifo_rx() argument
404 reg_val_GCR = readl(msp->registers + MSP_GCR); in flush_fifo_rx()
405 writel(reg_val_GCR | RX_ENABLE, msp->registers + MSP_GCR); in flush_fifo_rx()
407 reg_val_FLR = readl(msp->registers + MSP_FLR); in flush_fifo_rx()
409 reg_val_DR = readl(msp->registers + MSP_DR); in flush_fifo_rx()
410 reg_val_FLR = readl(msp->registers + MSP_FLR); in flush_fifo_rx()
413 writel(reg_val_GCR, msp->registers + MSP_GCR); in flush_fifo_rx()
416 static void flush_fifo_tx(struct ux500_msp *msp) in flush_fifo_tx() argument
421 reg_val_GCR = readl(msp->registers + MSP_GCR); in flush_fifo_tx()
422 writel(reg_val_GCR | TX_ENABLE, msp->registers + MSP_GCR); in flush_fifo_tx()
423 writel(MSP_ITCR_ITEN | MSP_ITCR_TESTFIFO, msp->registers + MSP_ITCR); in flush_fifo_tx()
425 reg_val_FLR = readl(msp->registers + MSP_FLR); in flush_fifo_tx()
427 reg_val_TSTDR = readl(msp->registers + MSP_TSTDR); in flush_fifo_tx()
428 reg_val_FLR = readl(msp->registers + MSP_FLR); in flush_fifo_tx()
430 writel(0x0, msp->registers + MSP_ITCR); in flush_fifo_tx()
431 writel(reg_val_GCR, msp->registers + MSP_GCR); in flush_fifo_tx()
434 int ux500_msp_i2s_open(struct ux500_msp *msp, in ux500_msp_i2s_open() argument
442 dev_err(msp->dev, in ux500_msp_i2s_open()
451 dev_err(msp->dev, "%s: Error: No direction selected!\n", in ux500_msp_i2s_open()
456 tx_busy = (msp->dir_busy & MSP_DIR_TX) > 0; in ux500_msp_i2s_open()
457 rx_busy = (msp->dir_busy & MSP_DIR_RX) > 0; in ux500_msp_i2s_open()
459 dev_err(msp->dev, "%s: Error: TX is in use!\n", __func__); in ux500_msp_i2s_open()
463 dev_err(msp->dev, "%s: Error: RX is in use!\n", __func__); in ux500_msp_i2s_open()
467 msp->dir_busy |= (tx_sel ? MSP_DIR_TX : 0) | (rx_sel ? MSP_DIR_RX : 0); in ux500_msp_i2s_open()
482 old_reg = readl(msp->registers + MSP_GCR); in ux500_msp_i2s_open()
485 writel(new_reg, msp->registers + MSP_GCR); in ux500_msp_i2s_open()
487 res = enable_msp(msp, config); in ux500_msp_i2s_open()
489 dev_err(msp->dev, "%s: ERROR: enable_msp failed (%d)!\n", in ux500_msp_i2s_open()
494 msp->loopback_enable = 1; in ux500_msp_i2s_open()
497 flush_fifo_tx(msp); in ux500_msp_i2s_open()
498 flush_fifo_rx(msp); in ux500_msp_i2s_open()
500 msp->msp_state = MSP_STATE_CONFIGURED; in ux500_msp_i2s_open()
504 static void disable_msp_rx(struct ux500_msp *msp) in disable_msp_rx() argument
508 reg_val_GCR = readl(msp->registers + MSP_GCR); in disable_msp_rx()
509 writel(reg_val_GCR & ~RX_ENABLE, msp->registers + MSP_GCR); in disable_msp_rx()
510 reg_val_DMACR = readl(msp->registers + MSP_DMACR); in disable_msp_rx()
511 writel(reg_val_DMACR & ~RX_DMA_ENABLE, msp->registers + MSP_DMACR); in disable_msp_rx()
512 reg_val_IMSC = readl(msp->registers + MSP_IMSC); in disable_msp_rx()
515 msp->registers + MSP_IMSC); in disable_msp_rx()
517 msp->dir_busy &= ~MSP_DIR_RX; in disable_msp_rx()
520 static void disable_msp_tx(struct ux500_msp *msp) in disable_msp_tx() argument
524 reg_val_GCR = readl(msp->registers + MSP_GCR); in disable_msp_tx()
525 writel(reg_val_GCR & ~TX_ENABLE, msp->registers + MSP_GCR); in disable_msp_tx()
526 reg_val_DMACR = readl(msp->registers + MSP_DMACR); in disable_msp_tx()
527 writel(reg_val_DMACR & ~TX_DMA_ENABLE, msp->registers + MSP_DMACR); in disable_msp_tx()
528 reg_val_IMSC = readl(msp->registers + MSP_IMSC); in disable_msp_tx()
531 msp->registers + MSP_IMSC); in disable_msp_tx()
533 msp->dir_busy &= ~MSP_DIR_TX; in disable_msp_tx()
536 static int disable_msp(struct ux500_msp *msp, unsigned int dir) in disable_msp() argument
542 reg_val_GCR = readl(msp->registers + MSP_GCR); in disable_msp()
546 reg_val_GCR = readl(msp->registers + MSP_GCR); in disable_msp()
548 msp->registers + MSP_GCR); in disable_msp()
551 flush_fifo_tx(msp); in disable_msp()
554 writel((readl(msp->registers + MSP_GCR) & in disable_msp()
555 (~TX_ENABLE)), msp->registers + MSP_GCR); in disable_msp()
558 flush_fifo_rx(msp); in disable_msp()
561 writel((readl(msp->registers + MSP_GCR) & in disable_msp()
563 msp->registers + MSP_GCR); in disable_msp()
565 disable_msp_tx(msp); in disable_msp()
566 disable_msp_rx(msp); in disable_msp()
568 disable_msp_tx(msp); in disable_msp()
570 disable_msp_rx(msp); in disable_msp()
575 int ux500_msp_i2s_trigger(struct ux500_msp *msp, int cmd, int direction) in ux500_msp_i2s_trigger() argument
579 if (msp->msp_state == MSP_STATE_IDLE) { in ux500_msp_i2s_trigger()
580 dev_err(msp->dev, "%s: ERROR: MSP is not configured!\n", in ux500_msp_i2s_trigger()
593 reg_val_GCR = readl(msp->registers + MSP_GCR); in ux500_msp_i2s_trigger()
594 writel(reg_val_GCR | enable_bit, msp->registers + MSP_GCR); in ux500_msp_i2s_trigger()
601 disable_msp_tx(msp); in ux500_msp_i2s_trigger()
603 disable_msp_rx(msp); in ux500_msp_i2s_trigger()
613 int ux500_msp_i2s_close(struct ux500_msp *msp, unsigned int dir) in ux500_msp_i2s_close() argument
617 dev_dbg(msp->dev, "%s: Enter (dir = 0x%01x).\n", __func__, dir); in ux500_msp_i2s_close()
619 status = disable_msp(msp, dir); in ux500_msp_i2s_close()
620 if (msp->dir_busy == 0) { in ux500_msp_i2s_close()
622 msp->msp_state = MSP_STATE_IDLE; in ux500_msp_i2s_close()
623 writel((readl(msp->registers + MSP_GCR) & in ux500_msp_i2s_close()
625 msp->registers + MSP_GCR); in ux500_msp_i2s_close()
627 writel(0, msp->registers + MSP_GCR); in ux500_msp_i2s_close()
628 writel(0, msp->registers + MSP_TCF); in ux500_msp_i2s_close()
629 writel(0, msp->registers + MSP_RCF); in ux500_msp_i2s_close()
630 writel(0, msp->registers + MSP_DMACR); in ux500_msp_i2s_close()
631 writel(0, msp->registers + MSP_SRG); in ux500_msp_i2s_close()
632 writel(0, msp->registers + MSP_MCR); in ux500_msp_i2s_close()
633 writel(0, msp->registers + MSP_RCM); in ux500_msp_i2s_close()
634 writel(0, msp->registers + MSP_RCV); in ux500_msp_i2s_close()
635 writel(0, msp->registers + MSP_TCE0); in ux500_msp_i2s_close()
636 writel(0, msp->registers + MSP_TCE1); in ux500_msp_i2s_close()
637 writel(0, msp->registers + MSP_TCE2); in ux500_msp_i2s_close()
638 writel(0, msp->registers + MSP_TCE3); in ux500_msp_i2s_close()
639 writel(0, msp->registers + MSP_RCE0); in ux500_msp_i2s_close()
640 writel(0, msp->registers + MSP_RCE1); in ux500_msp_i2s_close()
641 writel(0, msp->registers + MSP_RCE2); in ux500_msp_i2s_close()
642 writel(0, msp->registers + MSP_RCE3); in ux500_msp_i2s_close()
650 struct ux500_msp *msp, in ux500_msp_i2s_of_init_msp() argument
662 msp->playback_dma_data.dma_cfg = devm_kzalloc(&pdev->dev, in ux500_msp_i2s_of_init_msp()
665 if (!msp->playback_dma_data.dma_cfg) in ux500_msp_i2s_of_init_msp()
668 msp->capture_dma_data.dma_cfg = devm_kzalloc(&pdev->dev, in ux500_msp_i2s_of_init_msp()
671 if (!msp->capture_dma_data.dma_cfg) in ux500_msp_i2s_of_init_msp()
683 struct ux500_msp *msp; in ux500_msp_i2s_init_msp() local
687 msp = *msp_p; in ux500_msp_i2s_init_msp()
688 if (!msp) in ux500_msp_i2s_init_msp()
693 ret = ux500_msp_i2s_of_init_msp(pdev, msp, in ux500_msp_i2s_init_msp()
700 msp->playback_dma_data.dma_cfg = platform_data->msp_i2s_dma_tx; in ux500_msp_i2s_init_msp()
701 msp->capture_dma_data.dma_cfg = platform_data->msp_i2s_dma_rx; in ux500_msp_i2s_init_msp()
702 msp->id = platform_data->id; in ux500_msp_i2s_init_msp()
705 msp->dev = &pdev->dev; in ux500_msp_i2s_init_msp()
714 msp->playback_dma_data.tx_rx_addr = res->start + MSP_DR; in ux500_msp_i2s_init_msp()
715 msp->capture_dma_data.tx_rx_addr = res->start + MSP_DR; in ux500_msp_i2s_init_msp()
717 msp->registers = devm_ioremap(&pdev->dev, res->start, in ux500_msp_i2s_init_msp()
719 if (msp->registers == NULL) { in ux500_msp_i2s_init_msp()
724 msp->msp_state = MSP_STATE_IDLE; in ux500_msp_i2s_init_msp()
725 msp->loopback_enable = 0; in ux500_msp_i2s_init_msp()
731 struct ux500_msp *msp) in ux500_msp_i2s_cleanup_msp() argument
733 dev_dbg(msp->dev, "%s: Enter (id = %d).\n", __func__, msp->id); in ux500_msp_i2s_cleanup_msp()