37 	int err;  in tegra_asoc_utils_set_rate()  local
80 	err = clk_set_rate(data->clk_pll_a, new_baseclock);  in tegra_asoc_utils_set_rate()
81 	if (err) {  in tegra_asoc_utils_set_rate()
82 		dev_err(data->dev, "Can't set pll_a rate: %d\n", err);  in tegra_asoc_utils_set_rate()
83 		return err;  in tegra_asoc_utils_set_rate()
86 	err = clk_set_rate(data->clk_pll_a_out0, mclk);  in tegra_asoc_utils_set_rate()
87 	if (err) {  in tegra_asoc_utils_set_rate()
88 		dev_err(data->dev, "Can't set pll_a_out0 rate: %d\n", err);  in tegra_asoc_utils_set_rate()
89 		return err;  in tegra_asoc_utils_set_rate()
94 	err = clk_prepare_enable(data->clk_pll_a);  in tegra_asoc_utils_set_rate()
95 	if (err) {  in tegra_asoc_utils_set_rate()
96 		dev_err(data->dev, "Can't enable pll_a: %d\n", err);  in tegra_asoc_utils_set_rate()
97 		return err;  in tegra_asoc_utils_set_rate()
100 	err = clk_prepare_enable(data->clk_pll_a_out0);  in tegra_asoc_utils_set_rate()
101 	if (err) {  in tegra_asoc_utils_set_rate()
102 		dev_err(data->dev, "Can't enable pll_a_out0: %d\n", err);  in tegra_asoc_utils_set_rate()
103 		return err;  in tegra_asoc_utils_set_rate()
106 	err = clk_prepare_enable(data->clk_cdev1);  in tegra_asoc_utils_set_rate()
107 	if (err) {  in tegra_asoc_utils_set_rate()
108 		dev_err(data->dev, "Can't enable cdev1: %d\n", err);  in tegra_asoc_utils_set_rate()
109 		return err;  in tegra_asoc_utils_set_rate()
123 	int err;  in tegra_asoc_utils_set_ac97_rate()  local
133 	err = clk_set_rate(data->clk_pll_a, pll_rate);  in tegra_asoc_utils_set_ac97_rate()
134 	if (err) {  in tegra_asoc_utils_set_ac97_rate()
135 		dev_err(data->dev, "Can't set pll_a rate: %d\n", err);  in tegra_asoc_utils_set_ac97_rate()
136 		return err;  in tegra_asoc_utils_set_ac97_rate()
139 	err = clk_set_rate(data->clk_pll_a_out0, ac97_rate);  in tegra_asoc_utils_set_ac97_rate()
140 	if (err) {  in tegra_asoc_utils_set_ac97_rate()
141 		dev_err(data->dev, "Can't set pll_a_out0 rate: %d\n", err);  in tegra_asoc_utils_set_ac97_rate()
142 		return err;  in tegra_asoc_utils_set_ac97_rate()
147 	err = clk_prepare_enable(data->clk_pll_a);  in tegra_asoc_utils_set_ac97_rate()
148 	if (err) {  in tegra_asoc_utils_set_ac97_rate()
149 		dev_err(data->dev, "Can't enable pll_a: %d\n", err);  in tegra_asoc_utils_set_ac97_rate()
150 		return err;  in tegra_asoc_utils_set_ac97_rate()
153 	err = clk_prepare_enable(data->clk_pll_a_out0);  in tegra_asoc_utils_set_ac97_rate()
154 	if (err) {  in tegra_asoc_utils_set_ac97_rate()
155 		dev_err(data->dev, "Can't enable pll_a_out0: %d\n", err);  in tegra_asoc_utils_set_ac97_rate()
156 		return err;  in tegra_asoc_utils_set_ac97_rate()
159 	err = clk_prepare_enable(data->clk_cdev1);  in tegra_asoc_utils_set_ac97_rate()
160 	if (err) {  in tegra_asoc_utils_set_ac97_rate()
161 		dev_err(data->dev, "Can't enable cdev1: %d\n", err);  in tegra_asoc_utils_set_ac97_rate()
162 		return err;  in tegra_asoc_utils_set_ac97_rate()
196 		goto err;  in tegra_asoc_utils_init()
225 err:  in tegra_asoc_utils_init()