83 	dev_dbg(mcbsp->dev, "**** McBSP%d regs ****\n", mcbsp->id);  in omap_mcbsp_dump_reg()
84 	dev_dbg(mcbsp->dev, "DRR2:  0x%04x\n",  in omap_mcbsp_dump_reg()
86 	dev_dbg(mcbsp->dev, "DRR1:  0x%04x\n",  in omap_mcbsp_dump_reg()
88 	dev_dbg(mcbsp->dev, "DXR2:  0x%04x\n",  in omap_mcbsp_dump_reg()
90 	dev_dbg(mcbsp->dev, "DXR1:  0x%04x\n",  in omap_mcbsp_dump_reg()
92 	dev_dbg(mcbsp->dev, "SPCR2: 0x%04x\n",  in omap_mcbsp_dump_reg()
94 	dev_dbg(mcbsp->dev, "SPCR1: 0x%04x\n",  in omap_mcbsp_dump_reg()
96 	dev_dbg(mcbsp->dev, "RCR2:  0x%04x\n",  in omap_mcbsp_dump_reg()
98 	dev_dbg(mcbsp->dev, "RCR1:  0x%04x\n",  in omap_mcbsp_dump_reg()
100 	dev_dbg(mcbsp->dev, "XCR2:  0x%04x\n",  in omap_mcbsp_dump_reg()
102 	dev_dbg(mcbsp->dev, "XCR1:  0x%04x\n",  in omap_mcbsp_dump_reg()
104 	dev_dbg(mcbsp->dev, "SRGR2: 0x%04x\n",  in omap_mcbsp_dump_reg()
106 	dev_dbg(mcbsp->dev, "SRGR1: 0x%04x\n",  in omap_mcbsp_dump_reg()
108 	dev_dbg(mcbsp->dev, "PCR0:  0x%04x\n",  in omap_mcbsp_dump_reg()
110 	dev_dbg(mcbsp->dev, "***********************\n");  in omap_mcbsp_dump_reg()
119 	dev_dbg(mcbsp->dev, "IRQ callback : 0x%x\n", irqst);  in omap_mcbsp_irq_handler()
124 		dev_dbg(mcbsp->dev, "RX Frame Sync\n");  in omap_mcbsp_irq_handler()
126 		dev_dbg(mcbsp->dev, "RX End Of Frame\n");  in omap_mcbsp_irq_handler()
128 		dev_dbg(mcbsp->dev, "RX Buffer Threshold Reached\n");  in omap_mcbsp_irq_handler()
137 		dev_dbg(mcbsp->dev, "TX Frame Sync\n");  in omap_mcbsp_irq_handler()
139 		dev_dbg(mcbsp->dev, "TX End Of Frame\n");  in omap_mcbsp_irq_handler()
141 		dev_dbg(mcbsp->dev, "TX Buffer threshold Reached\n");  in omap_mcbsp_irq_handler()
147 		dev_dbg(mcbsp->dev, "TX Buffer empty at end of frame\n");  in omap_mcbsp_irq_handler()
160 	dev_dbg(mcbsp_tx->dev, "TX IRQ callback : 0x%x\n", irqst_spcr2);  in omap_mcbsp_tx_irq_handler()
178 	dev_dbg(mcbsp_rx->dev, "RX IRQ callback : 0x%x\n", irqst_spcr1);  in omap_mcbsp_rx_irq_handler()
199 	dev_dbg(mcbsp->dev, "Configuring McBSP%d  phys_base: 0x%08lx\n",  in omap_mcbsp_config()