Lines Matching refs:mcasp
70 struct davinci_mcasp *mcasp; member
112 static inline void mcasp_set_bits(struct davinci_mcasp *mcasp, u32 offset, in mcasp_set_bits() argument
115 void __iomem *reg = mcasp->base + offset; in mcasp_set_bits()
119 static inline void mcasp_clr_bits(struct davinci_mcasp *mcasp, u32 offset, in mcasp_clr_bits() argument
122 void __iomem *reg = mcasp->base + offset; in mcasp_clr_bits()
126 static inline void mcasp_mod_bits(struct davinci_mcasp *mcasp, u32 offset, in mcasp_mod_bits() argument
129 void __iomem *reg = mcasp->base + offset; in mcasp_mod_bits()
133 static inline void mcasp_set_reg(struct davinci_mcasp *mcasp, u32 offset, in mcasp_set_reg() argument
136 __raw_writel(val, mcasp->base + offset); in mcasp_set_reg()
139 static inline u32 mcasp_get_reg(struct davinci_mcasp *mcasp, u32 offset) in mcasp_get_reg() argument
141 return (u32)__raw_readl(mcasp->base + offset); in mcasp_get_reg()
144 static void mcasp_set_ctl_reg(struct davinci_mcasp *mcasp, u32 ctl_reg, u32 val) in mcasp_set_ctl_reg() argument
148 mcasp_set_bits(mcasp, ctl_reg, val); in mcasp_set_ctl_reg()
153 if ((mcasp_get_reg(mcasp, ctl_reg) & val) == val) in mcasp_set_ctl_reg()
157 if (i == 1000 && ((mcasp_get_reg(mcasp, ctl_reg) & val) != val)) in mcasp_set_ctl_reg()
161 static bool mcasp_is_synchronous(struct davinci_mcasp *mcasp) in mcasp_is_synchronous() argument
163 u32 rxfmctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXFMCTL_REG); in mcasp_is_synchronous()
164 u32 aclkxctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_ACLKXCTL_REG); in mcasp_is_synchronous()
169 static void mcasp_start_rx(struct davinci_mcasp *mcasp) in mcasp_start_rx() argument
171 if (mcasp->rxnumevt) { /* enable FIFO */ in mcasp_start_rx()
172 u32 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; in mcasp_start_rx()
174 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE); in mcasp_start_rx()
175 mcasp_set_bits(mcasp, reg, FIFO_ENABLE); in mcasp_start_rx()
179 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXHCLKRST); in mcasp_start_rx()
180 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXCLKRST); in mcasp_start_rx()
186 if (mcasp_is_synchronous(mcasp)) { in mcasp_start_rx()
187 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST); in mcasp_start_rx()
188 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST); in mcasp_start_rx()
192 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSERCLR); in mcasp_start_rx()
194 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSMRST); in mcasp_start_rx()
196 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXFSRST); in mcasp_start_rx()
197 if (mcasp_is_synchronous(mcasp)) in mcasp_start_rx()
198 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST); in mcasp_start_rx()
201 mcasp_set_bits(mcasp, DAVINCI_MCASP_EVTCTLR_REG, in mcasp_start_rx()
202 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]); in mcasp_start_rx()
205 static void mcasp_start_tx(struct davinci_mcasp *mcasp) in mcasp_start_tx() argument
209 if (mcasp->txnumevt) { /* enable FIFO */ in mcasp_start_tx()
210 u32 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; in mcasp_start_tx()
212 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE); in mcasp_start_tx()
213 mcasp_set_bits(mcasp, reg, FIFO_ENABLE); in mcasp_start_tx()
217 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST); in mcasp_start_tx()
218 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST); in mcasp_start_tx()
220 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSERCLR); in mcasp_start_tx()
224 while ((mcasp_get_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG) & XRDATA) && in mcasp_start_tx()
229 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSMRST); in mcasp_start_tx()
231 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST); in mcasp_start_tx()
234 mcasp_set_bits(mcasp, DAVINCI_MCASP_EVTCTLX_REG, in mcasp_start_tx()
235 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]); in mcasp_start_tx()
238 static void davinci_mcasp_start(struct davinci_mcasp *mcasp, int stream) in davinci_mcasp_start() argument
240 mcasp->streams++; in davinci_mcasp_start()
243 mcasp_start_tx(mcasp); in davinci_mcasp_start()
245 mcasp_start_rx(mcasp); in davinci_mcasp_start()
248 static void mcasp_stop_rx(struct davinci_mcasp *mcasp) in mcasp_stop_rx() argument
251 mcasp_clr_bits(mcasp, DAVINCI_MCASP_EVTCTLR_REG, in mcasp_stop_rx()
252 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]); in mcasp_stop_rx()
258 if (mcasp_is_synchronous(mcasp) && !mcasp->streams) in mcasp_stop_rx()
259 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, 0); in mcasp_stop_rx()
261 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, 0); in mcasp_stop_rx()
262 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF); in mcasp_stop_rx()
264 if (mcasp->rxnumevt) { /* disable FIFO */ in mcasp_stop_rx()
265 u32 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; in mcasp_stop_rx()
267 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE); in mcasp_stop_rx()
271 static void mcasp_stop_tx(struct davinci_mcasp *mcasp) in mcasp_stop_tx() argument
276 mcasp_clr_bits(mcasp, DAVINCI_MCASP_EVTCTLX_REG, in mcasp_stop_tx()
277 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]); in mcasp_stop_tx()
283 if (mcasp_is_synchronous(mcasp) && mcasp->streams) in mcasp_stop_tx()
286 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, val); in mcasp_stop_tx()
287 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF); in mcasp_stop_tx()
289 if (mcasp->txnumevt) { /* disable FIFO */ in mcasp_stop_tx()
290 u32 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; in mcasp_stop_tx()
292 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE); in mcasp_stop_tx()
296 static void davinci_mcasp_stop(struct davinci_mcasp *mcasp, int stream) in davinci_mcasp_stop() argument
298 mcasp->streams--; in davinci_mcasp_stop()
301 mcasp_stop_tx(mcasp); in davinci_mcasp_stop()
303 mcasp_stop_rx(mcasp); in davinci_mcasp_stop()
308 struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data; in davinci_mcasp_tx_irq_handler() local
310 u32 irq_mask = mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]; in davinci_mcasp_tx_irq_handler()
314 stat = mcasp_get_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG); in davinci_mcasp_tx_irq_handler()
316 dev_warn(mcasp->dev, "Transmit buffer underflow\n"); in davinci_mcasp_tx_irq_handler()
319 substream = mcasp->substreams[SNDRV_PCM_STREAM_PLAYBACK]; in davinci_mcasp_tx_irq_handler()
329 dev_warn(mcasp->dev, "unhandled tx event. txstat: 0x%08x\n", in davinci_mcasp_tx_irq_handler()
336 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, handled_mask); in davinci_mcasp_tx_irq_handler()
343 struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data; in davinci_mcasp_rx_irq_handler() local
345 u32 irq_mask = mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]; in davinci_mcasp_rx_irq_handler()
349 stat = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG); in davinci_mcasp_rx_irq_handler()
351 dev_warn(mcasp->dev, "Receive buffer overflow\n"); in davinci_mcasp_rx_irq_handler()
354 substream = mcasp->substreams[SNDRV_PCM_STREAM_CAPTURE]; in davinci_mcasp_rx_irq_handler()
364 dev_warn(mcasp->dev, "unhandled rx event. rxstat: 0x%08x\n", in davinci_mcasp_rx_irq_handler()
371 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, handled_mask); in davinci_mcasp_rx_irq_handler()
378 struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data; in davinci_mcasp_common_irq_handler() local
381 if (mcasp->substreams[SNDRV_PCM_STREAM_PLAYBACK]) in davinci_mcasp_common_irq_handler()
384 if (mcasp->substreams[SNDRV_PCM_STREAM_CAPTURE]) in davinci_mcasp_common_irq_handler()
393 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); in davinci_mcasp_set_dai_fmt() local
399 pm_runtime_get_sync(mcasp->dev); in davinci_mcasp_set_dai_fmt()
402 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR); in davinci_mcasp_set_dai_fmt()
403 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR); in davinci_mcasp_set_dai_fmt()
409 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR); in davinci_mcasp_set_dai_fmt()
410 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR); in davinci_mcasp_set_dai_fmt()
416 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR); in davinci_mcasp_set_dai_fmt()
417 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR); in davinci_mcasp_set_dai_fmt()
425 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR); in davinci_mcasp_set_dai_fmt()
426 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR); in davinci_mcasp_set_dai_fmt()
435 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, FSXDLY(data_delay), in davinci_mcasp_set_dai_fmt()
437 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, FSRDLY(data_delay), in davinci_mcasp_set_dai_fmt()
443 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE); in davinci_mcasp_set_dai_fmt()
444 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE); in davinci_mcasp_set_dai_fmt()
446 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE); in davinci_mcasp_set_dai_fmt()
447 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE); in davinci_mcasp_set_dai_fmt()
449 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR); in davinci_mcasp_set_dai_fmt()
450 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR); in davinci_mcasp_set_dai_fmt()
451 mcasp->bclk_master = 1; in davinci_mcasp_set_dai_fmt()
455 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE); in davinci_mcasp_set_dai_fmt()
456 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE); in davinci_mcasp_set_dai_fmt()
458 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE); in davinci_mcasp_set_dai_fmt()
459 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE); in davinci_mcasp_set_dai_fmt()
461 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR); in davinci_mcasp_set_dai_fmt()
462 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR); in davinci_mcasp_set_dai_fmt()
463 mcasp->bclk_master = 1; in davinci_mcasp_set_dai_fmt()
467 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE); in davinci_mcasp_set_dai_fmt()
468 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE); in davinci_mcasp_set_dai_fmt()
470 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE); in davinci_mcasp_set_dai_fmt()
471 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE); in davinci_mcasp_set_dai_fmt()
473 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR); in davinci_mcasp_set_dai_fmt()
474 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR); in davinci_mcasp_set_dai_fmt()
475 mcasp->bclk_master = 0; in davinci_mcasp_set_dai_fmt()
479 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE); in davinci_mcasp_set_dai_fmt()
480 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE); in davinci_mcasp_set_dai_fmt()
482 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE); in davinci_mcasp_set_dai_fmt()
483 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE); in davinci_mcasp_set_dai_fmt()
485 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, in davinci_mcasp_set_dai_fmt()
487 mcasp->bclk_master = 0; in davinci_mcasp_set_dai_fmt()
496 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); in davinci_mcasp_set_dai_fmt()
497 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); in davinci_mcasp_set_dai_fmt()
501 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); in davinci_mcasp_set_dai_fmt()
502 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); in davinci_mcasp_set_dai_fmt()
506 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); in davinci_mcasp_set_dai_fmt()
507 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); in davinci_mcasp_set_dai_fmt()
511 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); in davinci_mcasp_set_dai_fmt()
512 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); in davinci_mcasp_set_dai_fmt()
524 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL); in davinci_mcasp_set_dai_fmt()
525 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL); in davinci_mcasp_set_dai_fmt()
527 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL); in davinci_mcasp_set_dai_fmt()
528 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL); in davinci_mcasp_set_dai_fmt()
531 pm_runtime_put(mcasp->dev); in davinci_mcasp_set_dai_fmt()
538 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); in __davinci_mcasp_set_clkdiv() local
540 pm_runtime_get_sync(mcasp->dev); in __davinci_mcasp_set_clkdiv()
543 mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, in __davinci_mcasp_set_clkdiv()
545 mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, in __davinci_mcasp_set_clkdiv()
550 mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, in __davinci_mcasp_set_clkdiv()
552 mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, in __davinci_mcasp_set_clkdiv()
555 mcasp->bclk_div = div; in __davinci_mcasp_set_clkdiv()
559 mcasp->bclk_lrclk_ratio = div; in __davinci_mcasp_set_clkdiv()
566 pm_runtime_put(mcasp->dev); in __davinci_mcasp_set_clkdiv()
579 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); in davinci_mcasp_set_sysclk() local
581 pm_runtime_get_sync(mcasp->dev); in davinci_mcasp_set_sysclk()
583 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE); in davinci_mcasp_set_sysclk()
584 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE); in davinci_mcasp_set_sysclk()
585 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AHCLKX); in davinci_mcasp_set_sysclk()
587 mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE); in davinci_mcasp_set_sysclk()
588 mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE); in davinci_mcasp_set_sysclk()
589 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AHCLKX); in davinci_mcasp_set_sysclk()
592 mcasp->sysclk_freq = freq; in davinci_mcasp_set_sysclk()
594 pm_runtime_put(mcasp->dev); in davinci_mcasp_set_sysclk()
598 static int davinci_config_channel_size(struct davinci_mcasp *mcasp, in davinci_config_channel_size() argument
624 if (mcasp->bclk_lrclk_ratio) { in davinci_config_channel_size()
625 u32 slot_length = mcasp->bclk_lrclk_ratio / mcasp->tdm_slots; in davinci_config_channel_size()
639 if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) { in davinci_config_channel_size()
640 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXSSZ(fmt), in davinci_config_channel_size()
642 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXSSZ(fmt), in davinci_config_channel_size()
644 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(tx_rotate), in davinci_config_channel_size()
646 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXROT(rx_rotate), in davinci_config_channel_size()
648 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXMASK_REG, mask); in davinci_config_channel_size()
651 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXMASK_REG, mask); in davinci_config_channel_size()
656 static int mcasp_common_hw_param(struct davinci_mcasp *mcasp, int stream, in mcasp_common_hw_param() argument
659 struct snd_dmaengine_dai_dma_data *dma_data = &mcasp->dma_data[stream]; in mcasp_common_hw_param()
663 u8 slots = mcasp->tdm_slots; in mcasp_common_hw_param()
668 if (mcasp->version < MCASP_VERSION_3) in mcasp_common_hw_param()
669 mcasp_set_bits(mcasp, DAVINCI_MCASP_PWREMUMGT_REG, MCASP_SOFT); in mcasp_common_hw_param()
672 mcasp_set_reg(mcasp, DAVINCI_MCASP_PFUNC_REG, 0x00000000); in mcasp_common_hw_param()
675 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF); in mcasp_common_hw_param()
676 mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS); in mcasp_common_hw_param()
678 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF); in mcasp_common_hw_param()
679 mcasp_clr_bits(mcasp, DAVINCI_MCASP_REVTCTL_REG, RXDATADMADIS); in mcasp_common_hw_param()
682 for (i = 0; i < mcasp->num_serializer; i++) { in mcasp_common_hw_param()
683 mcasp_set_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i), in mcasp_common_hw_param()
684 mcasp->serial_dir[i]); in mcasp_common_hw_param()
685 if (mcasp->serial_dir[i] == TX_MODE && in mcasp_common_hw_param()
687 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AXR(i)); in mcasp_common_hw_param()
689 } else if (mcasp->serial_dir[i] == RX_MODE && in mcasp_common_hw_param()
691 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AXR(i)); in mcasp_common_hw_param()
694 mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i), in mcasp_common_hw_param()
701 numevt = mcasp->txnumevt; in mcasp_common_hw_param()
702 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; in mcasp_common_hw_param()
705 numevt = mcasp->rxnumevt; in mcasp_common_hw_param()
706 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; in mcasp_common_hw_param()
710 dev_warn(mcasp->dev, "stream has more channels (%d) than are " in mcasp_common_hw_param()
734 dev_err(mcasp->dev, "Invalid combination of period words and " in mcasp_common_hw_param()
753 mcasp_mod_bits(mcasp, reg, active_serializers, NUMDMA_MASK); in mcasp_common_hw_param()
754 mcasp_mod_bits(mcasp, reg, NUMEVT(numevt), NUMEVT_MASK); in mcasp_common_hw_param()
764 static int mcasp_i2s_hw_param(struct davinci_mcasp *mcasp, int stream, in mcasp_i2s_hw_param() argument
773 total_slots = mcasp->tdm_slots; in mcasp_i2s_hw_param()
790 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, TX_ASYNC); in mcasp_i2s_hw_param()
792 if (!mcasp->dat_port) in mcasp_i2s_hw_param()
795 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, mask); in mcasp_i2s_hw_param()
796 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, busel | TXORD); in mcasp_i2s_hw_param()
797 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, in mcasp_i2s_hw_param()
800 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXTDM_REG, mask); in mcasp_i2s_hw_param()
801 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, busel | RXORD); in mcasp_i2s_hw_param()
802 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, in mcasp_i2s_hw_param()
809 static int mcasp_dit_hw_param(struct davinci_mcasp *mcasp, in mcasp_dit_hw_param() argument
817 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(6) | TXSSZ(15)); in mcasp_dit_hw_param()
820 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE | FSXMOD(0x180)); in mcasp_dit_hw_param()
823 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, 0xFFFFFFFF); in mcasp_dit_hw_param()
826 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE | TX_ASYNC); in mcasp_dit_hw_param()
828 mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS); in mcasp_dit_hw_param()
831 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXDIV(3)); in mcasp_dit_hw_param()
834 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXDITCTL_REG, DITEN); in mcasp_dit_hw_param()
873 mcasp_set_reg(mcasp, DAVINCI_MCASP_DITCSRA_REG, cs_value); in mcasp_dit_hw_param()
874 mcasp_set_reg(mcasp, DAVINCI_MCASP_DITCSRB_REG, cs_value); in mcasp_dit_hw_param()
879 static int davinci_mcasp_calc_clk_div(struct davinci_mcasp *mcasp, in davinci_mcasp_calc_clk_div() argument
883 int div = mcasp->sysclk_freq / bclk_freq; in davinci_mcasp_calc_clk_div()
884 int rem = mcasp->sysclk_freq % bclk_freq; in davinci_mcasp_calc_clk_div()
888 ((mcasp->sysclk_freq / div) - bclk_freq) > in davinci_mcasp_calc_clk_div()
889 (bclk_freq - (mcasp->sysclk_freq / (div+1)))) { in davinci_mcasp_calc_clk_div()
907 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); in davinci_mcasp_hw_params() local
917 if (mcasp->bclk_master && mcasp->bclk_div == 0 && mcasp->sysclk_freq) { in davinci_mcasp_hw_params()
923 if (channels > mcasp->tdm_slots) in davinci_mcasp_hw_params()
924 channels = mcasp->tdm_slots; in davinci_mcasp_hw_params()
926 div = davinci_mcasp_calc_clk_div(mcasp, rate*sbits*channels, in davinci_mcasp_hw_params()
929 dev_info(mcasp->dev, "Sample-rate is off by %d PPM\n", in davinci_mcasp_hw_params()
935 ret = mcasp_common_hw_param(mcasp, substream->stream, in davinci_mcasp_hw_params()
940 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE) in davinci_mcasp_hw_params()
941 ret = mcasp_dit_hw_param(mcasp, params_rate(params)); in davinci_mcasp_hw_params()
943 ret = mcasp_i2s_hw_param(mcasp, substream->stream, in davinci_mcasp_hw_params()
980 davinci_config_channel_size(mcasp, word_length); in davinci_mcasp_hw_params()
982 if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE) in davinci_mcasp_hw_params()
983 mcasp->channels = channels; in davinci_mcasp_hw_params()
991 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); in davinci_mcasp_trigger() local
998 davinci_mcasp_start(mcasp, substream->stream); in davinci_mcasp_trigger()
1003 davinci_mcasp_stop(mcasp, substream->stream); in davinci_mcasp_trigger()
1031 if (channels > rd->mcasp->tdm_slots) in davinci_mcasp_hw_rule_rate()
1032 channels = rd->mcasp->tdm_slots; in davinci_mcasp_hw_rule_rate()
1041 davinci_mcasp_calc_clk_div(rd->mcasp, bclk_freq, &ppm); in davinci_mcasp_hw_rule_rate()
1046 dev_dbg(rd->mcasp->dev, in davinci_mcasp_hw_rule_rate()
1066 if (channels > rd->mcasp->tdm_slots) in davinci_mcasp_hw_rule_format()
1067 channels = rd->mcasp->tdm_slots; in davinci_mcasp_hw_rule_format()
1074 davinci_mcasp_calc_clk_div(rd->mcasp, bclk_freq, &ppm); in davinci_mcasp_hw_rule_format()
1081 dev_dbg(rd->mcasp->dev, in davinci_mcasp_hw_rule_format()
1096 int max_chan_per_wire = rd->mcasp->tdm_slots < ci->max ? in davinci_mcasp_hw_rule_channels()
1097 rd->mcasp->tdm_slots : ci->max; in davinci_mcasp_hw_rule_channels()
1105 davinci_mcasp_calc_clk_div(rd->mcasp, bclk_freq, &ppm); in davinci_mcasp_hw_rule_channels()
1110 if (c1 == rd->mcasp->tdm_slots) { in davinci_mcasp_hw_rule_channels()
1119 dev_dbg(rd->mcasp->dev, in davinci_mcasp_hw_rule_channels()
1130 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); in davinci_mcasp_startup() local
1132 &mcasp->ruledata[substream->stream]; in davinci_mcasp_startup()
1136 mcasp->substreams[substream->stream] = substream; in davinci_mcasp_startup()
1138 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE) in davinci_mcasp_startup()
1150 for (i = 0; i < mcasp->num_serializer; i++) { in davinci_mcasp_startup()
1151 if (mcasp->serial_dir[i] == dir) in davinci_mcasp_startup()
1155 max_channels *= mcasp->tdm_slots; in davinci_mcasp_startup()
1163 if (mcasp->channels && mcasp->channels < max_channels) in davinci_mcasp_startup()
1164 max_channels = mcasp->channels; in davinci_mcasp_startup()
1174 if (mcasp->bclk_master && mcasp->bclk_div == 0 && mcasp->sysclk_freq) { in davinci_mcasp_startup()
1177 ruledata->mcasp = mcasp; in davinci_mcasp_startup()
1211 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); in davinci_mcasp_shutdown() local
1213 mcasp->substreams[substream->stream] = NULL; in davinci_mcasp_shutdown()
1215 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE) in davinci_mcasp_shutdown()
1219 mcasp->channels = 0; in davinci_mcasp_shutdown()
1234 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); in davinci_mcasp_dai_probe() local
1236 dai->playback_dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK]; in davinci_mcasp_dai_probe()
1237 dai->capture_dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE]; in davinci_mcasp_dai_probe()
1245 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); in davinci_mcasp_suspend() local
1246 struct davinci_mcasp_context *context = &mcasp->context; in davinci_mcasp_suspend()
1250 context->pm_state = pm_runtime_active(mcasp->dev); in davinci_mcasp_suspend()
1252 pm_runtime_get_sync(mcasp->dev); in davinci_mcasp_suspend()
1255 context->config_regs[i] = mcasp_get_reg(mcasp, context_regs[i]); in davinci_mcasp_suspend()
1257 if (mcasp->txnumevt) { in davinci_mcasp_suspend()
1258 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; in davinci_mcasp_suspend()
1259 context->afifo_regs[0] = mcasp_get_reg(mcasp, reg); in davinci_mcasp_suspend()
1261 if (mcasp->rxnumevt) { in davinci_mcasp_suspend()
1262 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; in davinci_mcasp_suspend()
1263 context->afifo_regs[1] = mcasp_get_reg(mcasp, reg); in davinci_mcasp_suspend()
1266 for (i = 0; i < mcasp->num_serializer; i++) in davinci_mcasp_suspend()
1267 context->xrsr_regs[i] = mcasp_get_reg(mcasp, in davinci_mcasp_suspend()
1270 pm_runtime_put_sync(mcasp->dev); in davinci_mcasp_suspend()
1277 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); in davinci_mcasp_resume() local
1278 struct davinci_mcasp_context *context = &mcasp->context; in davinci_mcasp_resume()
1282 pm_runtime_get_sync(mcasp->dev); in davinci_mcasp_resume()
1285 mcasp_set_reg(mcasp, context_regs[i], context->config_regs[i]); in davinci_mcasp_resume()
1287 if (mcasp->txnumevt) { in davinci_mcasp_resume()
1288 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; in davinci_mcasp_resume()
1289 mcasp_set_reg(mcasp, reg, context->afifo_regs[0]); in davinci_mcasp_resume()
1291 if (mcasp->rxnumevt) { in davinci_mcasp_resume()
1292 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; in davinci_mcasp_resume()
1293 mcasp_set_reg(mcasp, reg, context->afifo_regs[1]); in davinci_mcasp_resume()
1296 for (i = 0; i < mcasp->num_serializer; i++) in davinci_mcasp_resume()
1297 mcasp_set_reg(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i), in davinci_mcasp_resume()
1301 pm_runtime_put_sync(mcasp->dev); in davinci_mcasp_resume()
1564 struct davinci_mcasp *mcasp; in davinci_mcasp_probe() local
1575 mcasp = devm_kzalloc(&pdev->dev, sizeof(struct davinci_mcasp), in davinci_mcasp_probe()
1577 if (!mcasp) in davinci_mcasp_probe()
1588 dev_warn(mcasp->dev, in davinci_mcasp_probe()
1606 mcasp->base = devm_ioremap(&pdev->dev, mem->start, resource_size(mem)); in davinci_mcasp_probe()
1607 if (!mcasp->base) { in davinci_mcasp_probe()
1613 mcasp->op_mode = pdata->op_mode; in davinci_mcasp_probe()
1615 if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE) { in davinci_mcasp_probe()
1619 mcasp->tdm_slots = 2; in davinci_mcasp_probe()
1623 mcasp->tdm_slots = 32; in davinci_mcasp_probe()
1625 mcasp->tdm_slots = pdata->tdm_slots; in davinci_mcasp_probe()
1629 mcasp->num_serializer = pdata->num_serializer; in davinci_mcasp_probe()
1631 mcasp->context.xrsr_regs = devm_kzalloc(&pdev->dev, in davinci_mcasp_probe()
1632 sizeof(u32) * mcasp->num_serializer, in davinci_mcasp_probe()
1635 mcasp->serial_dir = pdata->serial_dir; in davinci_mcasp_probe()
1636 mcasp->version = pdata->version; in davinci_mcasp_probe()
1637 mcasp->txnumevt = pdata->txnumevt; in davinci_mcasp_probe()
1638 mcasp->rxnumevt = pdata->rxnumevt; in davinci_mcasp_probe()
1640 mcasp->dev = &pdev->dev; in davinci_mcasp_probe()
1649 irq_name, mcasp); in davinci_mcasp_probe()
1655 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK] = XUNDRN; in davinci_mcasp_probe()
1656 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE] = ROVRN; in davinci_mcasp_probe()
1665 IRQF_ONESHOT, irq_name, mcasp); in davinci_mcasp_probe()
1671 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE] = ROVRN; in davinci_mcasp_probe()
1680 IRQF_ONESHOT, irq_name, mcasp); in davinci_mcasp_probe()
1686 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK] = XUNDRN; in davinci_mcasp_probe()
1691 mcasp->dat_port = true; in davinci_mcasp_probe()
1693 dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK]; in davinci_mcasp_probe()
1699 dma = &mcasp->dma_request[SNDRV_PCM_STREAM_PLAYBACK]; in davinci_mcasp_probe()
1713 if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) { in davinci_mcasp_probe()
1714 dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE]; in davinci_mcasp_probe()
1720 dma = &mcasp->dma_request[SNDRV_PCM_STREAM_CAPTURE]; in davinci_mcasp_probe()
1734 if (mcasp->version < MCASP_VERSION_3) { in davinci_mcasp_probe()
1735 mcasp->fifo_base = DAVINCI_MCASP_V2_AFIFO_BASE; in davinci_mcasp_probe()
1737 mcasp->dat_port = true; in davinci_mcasp_probe()
1739 mcasp->fifo_base = DAVINCI_MCASP_V3_AFIFO_BASE; in davinci_mcasp_probe()
1742 dev_set_drvdata(&pdev->dev, mcasp); in davinci_mcasp_probe()
1753 switch (mcasp->version) { in davinci_mcasp_probe()
1772 mcasp->version); in davinci_mcasp_probe()