Lines Matching refs:clk_ctl
561 int clk_ctl = 0; in sgtl5000_set_clock() local
586 clk_ctl |= SGTL5000_RATE_MODE_DIV_4 << SGTL5000_RATE_MODE_SHIFT; in sgtl5000_set_clock()
589 clk_ctl |= SGTL5000_RATE_MODE_DIV_2 << SGTL5000_RATE_MODE_SHIFT; in sgtl5000_set_clock()
592 clk_ctl |= SGTL5000_RATE_MODE_DIV_1 << SGTL5000_RATE_MODE_SHIFT; in sgtl5000_set_clock()
601 clk_ctl |= SGTL5000_SYS_FS_32k << SGTL5000_SYS_FS_SHIFT; in sgtl5000_set_clock()
604 clk_ctl |= SGTL5000_SYS_FS_44_1k << SGTL5000_SYS_FS_SHIFT; in sgtl5000_set_clock()
607 clk_ctl |= SGTL5000_SYS_FS_48k << SGTL5000_SYS_FS_SHIFT; in sgtl5000_set_clock()
610 clk_ctl |= SGTL5000_SYS_FS_96k << SGTL5000_SYS_FS_SHIFT; in sgtl5000_set_clock()
625 clk_ctl |= SGTL5000_MCLK_FREQ_256FS << in sgtl5000_set_clock()
629 clk_ctl |= SGTL5000_MCLK_FREQ_384FS << in sgtl5000_set_clock()
633 clk_ctl |= SGTL5000_MCLK_FREQ_512FS << in sgtl5000_set_clock()
639 clk_ctl |= SGTL5000_MCLK_FREQ_PLL << in sgtl5000_set_clock()
652 if ((clk_ctl & SGTL5000_MCLK_FREQ_MASK) == SGTL5000_MCLK_FREQ_PLL) { in sgtl5000_set_clock()
695 snd_soc_write(codec, SGTL5000_CHIP_CLK_CTRL, clk_ctl); in sgtl5000_set_clock()
698 snd_soc_write(codec, SGTL5000_CHIP_CLK_CTRL, clk_ctl); in sgtl5000_set_clock()