2971 static void alc5505_coef_set(struct hda_codec *codec, unsigned int index_reg,  in alc5505_coef_set()  function
2995 	alc5505_coef_set(codec, 0x3000, 0x000c); /* DSP CPU stop */  in alc5505_dsp_halt()
2996 	alc5505_coef_set(codec, 0x880c, 0x0008); /* DDR enter self refresh */  in alc5505_dsp_halt()
2997 	alc5505_coef_set(codec, 0x61c0, 0x11110080); /* Clock control for PLL and CPU */  in alc5505_dsp_halt()
2998 	alc5505_coef_set(codec, 0x6230, 0xfc0d4011); /* Disable Input OP */  in alc5505_dsp_halt()
2999 	alc5505_coef_set(codec, 0x61b4, 0x040a2b03); /* Stop PLL2 */  in alc5505_dsp_halt()
3000 	alc5505_coef_set(codec, 0x61b0, 0x00005b17); /* Stop PLL1 */  in alc5505_dsp_halt()
3001 	alc5505_coef_set(codec, 0x61b8, 0x04133303); /* Stop PLL3 */  in alc5505_dsp_halt()
3003 	alc5505_coef_set(codec, 0x6220, (val | 0x3000)); /* switch Ringbuffer clock to DBUS clock */  in alc5505_dsp_halt()
3008 	alc5505_coef_set(codec, 0x61b8, 0x04133302);  in alc5505_dsp_back_from_halt()
3009 	alc5505_coef_set(codec, 0x61b0, 0x00005b16);  in alc5505_dsp_back_from_halt()
3010 	alc5505_coef_set(codec, 0x61b4, 0x040a2b02);  in alc5505_dsp_back_from_halt()
3011 	alc5505_coef_set(codec, 0x6230, 0xf80d4011);  in alc5505_dsp_back_from_halt()
3012 	alc5505_coef_set(codec, 0x6220, 0x2002010f);  in alc5505_dsp_back_from_halt()
3013 	alc5505_coef_set(codec, 0x880c, 0x00000004);  in alc5505_dsp_back_from_halt()
3022 	alc5505_coef_set(codec, 0x61b0, 0x5b14); /* PLL1 control */  in alc5505_dsp_init()
3023 	alc5505_coef_set(codec, 0x61b0, 0x5b16);  in alc5505_dsp_init()
3024 	alc5505_coef_set(codec, 0x61b4, 0x04132b00); /* PLL2 control */  in alc5505_dsp_init()
3025 	alc5505_coef_set(codec, 0x61b4, 0x04132b02);  in alc5505_dsp_init()
3026 	alc5505_coef_set(codec, 0x61b8, 0x041f3300); /* PLL3 control*/  in alc5505_dsp_init()
3027 	alc5505_coef_set(codec, 0x61b8, 0x041f3302);  in alc5505_dsp_init()
3029 	alc5505_coef_set(codec, 0x61b8, 0x041b3302);  in alc5505_dsp_init()
3030 	alc5505_coef_set(codec, 0x61b8, 0x04173302);  in alc5505_dsp_init()
3031 	alc5505_coef_set(codec, 0x61b8, 0x04163302);  in alc5505_dsp_init()
3032 	alc5505_coef_set(codec, 0x8800, 0x348b328b); /* DRAM control */  in alc5505_dsp_init()
3033 	alc5505_coef_set(codec, 0x8808, 0x00020022); /* DRAM control */  in alc5505_dsp_init()
3034 	alc5505_coef_set(codec, 0x8818, 0x00000400); /* DRAM control */  in alc5505_dsp_init()
3038 		alc5505_coef_set(codec, 0x6220, 0x2002010f); /* I/O PAD Configuration */  in alc5505_dsp_init()
3040 		alc5505_coef_set(codec, 0x6220, 0x6002018f);  in alc5505_dsp_init()
3042 	alc5505_coef_set(codec, 0x61ac, 0x055525f0); /**/  in alc5505_dsp_init()
3043 	alc5505_coef_set(codec, 0x61c0, 0x12230080); /* Clock control */  in alc5505_dsp_init()
3044 	alc5505_coef_set(codec, 0x61b4, 0x040e2b02); /* PLL2 control */  in alc5505_dsp_init()
3045 	alc5505_coef_set(codec, 0x61bc, 0x010234f8); /* OSC Control */  in alc5505_dsp_init()
3046 	alc5505_coef_set(codec, 0x880c, 0x00000004); /* DRAM Function control */  in alc5505_dsp_init()
3047 	alc5505_coef_set(codec, 0x880c, 0x00000003);  in alc5505_dsp_init()
3048 	alc5505_coef_set(codec, 0x880c, 0x00000010);  in alc5505_dsp_init()