1035 	chip->rirb.addr = chip->rb.addr + 2048;  in azx_init_cmd_io()
1036 	chip->rirb.buf = (u32 *)(chip->rb.area + 2048);  in azx_init_cmd_io()
1037 	chip->rirb.wp = chip->rirb.rp = 0;  in azx_init_cmd_io()
1038 	memset(chip->rirb.cmds, 0, sizeof(chip->rirb.cmds));  in azx_init_cmd_io()
1039 	azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);  in azx_init_cmd_io()
1040 	azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));  in azx_init_cmd_io()
1103 	chip->rirb.cmds[addr]++;  in azx_corb_send_cmd()
1127 	if (wp == chip->rirb.wp)  in azx_update_rirb()
1129 	chip->rirb.wp = wp;  in azx_update_rirb()
1131 	while (chip->rirb.rp != wp) {  in azx_update_rirb()
1132 		chip->rirb.rp++;  in azx_update_rirb()
1133 		chip->rirb.rp %= AZX_MAX_RIRB_ENTRIES;  in azx_update_rirb()
1135 		rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */  in azx_update_rirb()
1136 		res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);  in azx_update_rirb()
1137 		res = le32_to_cpu(chip->rirb.buf[rp]);  in azx_update_rirb()
1142 				chip->rirb.rp, wp);  in azx_update_rirb()
1146 		else if (chip->rirb.cmds[addr]) {  in azx_update_rirb()
1147 			chip->rirb.res[addr] = res;  in azx_update_rirb()
1149 			chip->rirb.cmds[addr]--;  in azx_update_rirb()
1176 		if (!chip->rirb.cmds[addr]) {  in azx_rirb_get_response()
1182 			return chip->rirb.res[addr]; /* the last value */  in azx_rirb_get_response()
1275 			chip->rirb.res[addr] = azx_readl(chip, IR);  in azx_single_wait_for_response()
1283 	chip->rirb.res[addr] = -1;  in azx_single_wait_for_response()
1320 	return chip->rirb.res[addr];  in azx_single_get_response()