Lines Matching refs:chip
55 static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev) in azx_stream_start() argument
63 azx_writel(chip, INTCTL, in azx_stream_start()
64 azx_readl(chip, INTCTL) | (1 << azx_dev->index)); in azx_stream_start()
66 azx_sd_writeb(chip, azx_dev, SD_CTL, in azx_stream_start()
67 azx_sd_readb(chip, azx_dev, SD_CTL) | in azx_stream_start()
72 static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev) in azx_stream_clear() argument
74 azx_sd_writeb(chip, azx_dev, SD_CTL, in azx_stream_clear()
75 azx_sd_readb(chip, azx_dev, SD_CTL) & in azx_stream_clear()
77 azx_sd_writeb(chip, azx_dev, SD_STS, SD_INT_MASK); /* to be sure */ in azx_stream_clear()
81 void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev) in azx_stream_stop() argument
83 azx_stream_clear(chip, azx_dev); in azx_stream_stop()
85 azx_writel(chip, INTCTL, in azx_stream_stop()
86 azx_readl(chip, INTCTL) & ~(1 << azx_dev->index)); in azx_stream_stop()
91 static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev) in azx_stream_reset() argument
96 azx_stream_clear(chip, azx_dev); in azx_stream_reset()
98 azx_sd_writeb(chip, azx_dev, SD_CTL, in azx_stream_reset()
99 azx_sd_readb(chip, azx_dev, SD_CTL) | in azx_stream_reset()
103 while (!((val = azx_sd_readb(chip, azx_dev, SD_CTL)) & in azx_stream_reset()
107 azx_sd_writeb(chip, azx_dev, SD_CTL, val); in azx_stream_reset()
112 while (((val = azx_sd_readb(chip, azx_dev, SD_CTL)) & in azx_stream_reset()
123 static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev) in azx_setup_controller() argument
127 azx_stream_clear(chip, azx_dev); in azx_setup_controller()
129 val = azx_sd_readl(chip, azx_dev, SD_CTL); in azx_setup_controller()
132 if (!azx_snoop(chip)) in azx_setup_controller()
134 azx_sd_writel(chip, azx_dev, SD_CTL, val); in azx_setup_controller()
137 azx_sd_writel(chip, azx_dev, SD_CBL, azx_dev->bufsize); in azx_setup_controller()
141 azx_sd_writew(chip, azx_dev, SD_FORMAT, azx_dev->format_val); in azx_setup_controller()
144 azx_sd_writew(chip, azx_dev, SD_LVI, azx_dev->frags - 1); in azx_setup_controller()
148 azx_sd_writel(chip, azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr); in azx_setup_controller()
150 azx_sd_writel(chip, azx_dev, SD_BDLPU, in azx_setup_controller()
154 if (chip->get_position[0] != azx_get_pos_lpib || in azx_setup_controller()
155 chip->get_position[1] != azx_get_pos_lpib) { in azx_setup_controller()
156 if (!(azx_readl(chip, DPLBASE) & AZX_DPLBASE_ENABLE)) in azx_setup_controller()
157 azx_writel(chip, DPLBASE, in azx_setup_controller()
158 (u32)chip->posbuf.addr | AZX_DPLBASE_ENABLE); in azx_setup_controller()
162 azx_sd_writel(chip, azx_dev, SD_CTL, in azx_setup_controller()
163 azx_sd_readl(chip, azx_dev, SD_CTL) | SD_INT_MASK); in azx_setup_controller()
170 azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream) in azx_assign_device() argument
179 dev = chip->playback_index_offset; in azx_assign_device()
180 nums = chip->playback_streams; in azx_assign_device()
182 dev = chip->capture_index_offset; in azx_assign_device()
183 nums = chip->capture_streams; in azx_assign_device()
186 struct azx_dev *azx_dev = &chip->azx_dev[dev]; in azx_assign_device()
196 (chip->driver_caps & AZX_DCAPS_REVERSE_ASSIGN)) in azx_assign_device()
221 struct azx *chip = apcm->chip; in azx_cc_read() local
223 return azx_readl(chip, WALLCLK); in azx_cc_read()
290 static int setup_bdle(struct azx *chip, in setup_bdle() argument
311 if (chip->driver_caps & AZX_DCAPS_4K_BDLE_BOUNDARY) { in setup_bdle()
333 static int azx_setup_periods(struct azx *chip, in azx_setup_periods() argument
342 azx_sd_writel(chip, azx_dev, SD_BDLPL, 0); in azx_setup_periods()
343 azx_sd_writel(chip, azx_dev, SD_BDLPU, 0); in azx_setup_periods()
353 if (chip->bdl_pos_adj) in azx_setup_periods()
354 pos_adj = chip->bdl_pos_adj[chip->dev_index]; in azx_setup_periods()
366 dev_warn(chip->card->dev,"Too big adjustment %d\n", in azx_setup_periods()
370 ofs = setup_bdle(chip, snd_pcm_get_dma_buf(substream), in azx_setup_periods()
381 ofs = setup_bdle(chip, snd_pcm_get_dma_buf(substream), in azx_setup_periods()
385 ofs = setup_bdle(chip, snd_pcm_get_dma_buf(substream), in azx_setup_periods()
395 dev_err(chip->card->dev, "Too many BDL entries: buffer=%d, period=%d\n", in azx_setup_periods()
408 struct azx *chip = apcm->chip; in azx_pcm_close() local
412 mutex_lock(&chip->open_mutex); in azx_pcm_close()
413 spin_lock_irqsave(&chip->reg_lock, flags); in azx_pcm_close()
416 spin_unlock_irqrestore(&chip->reg_lock, flags); in azx_pcm_close()
421 mutex_unlock(&chip->open_mutex); in azx_pcm_close()
430 struct azx *chip = apcm->chip; in azx_pcm_hw_params() local
439 ret = chip->ops->substream_alloc_pages(chip, substream, in azx_pcm_hw_params()
450 struct azx *chip = apcm->chip; in azx_pcm_hw_free() local
457 azx_sd_writel(chip, azx_dev, SD_BDLPL, 0); in azx_pcm_hw_free()
458 azx_sd_writel(chip, azx_dev, SD_BDLPU, 0); in azx_pcm_hw_free()
459 azx_sd_writel(chip, azx_dev, SD_CTL, 0); in azx_pcm_hw_free()
467 err = chip->ops->substream_free_pages(chip, substream); in azx_pcm_hw_free()
476 struct azx *chip = apcm->chip; in azx_pcm_prepare() local
492 azx_stream_reset(chip, azx_dev); in azx_pcm_prepare()
500 dev_err(chip->card->dev, in azx_pcm_prepare()
510 dev_dbg(chip->card->dev, "azx_pcm_prepare: bufsize=0x%x, format=0x%x\n", in azx_pcm_prepare()
521 err = azx_setup_periods(chip, substream, azx_dev); in azx_pcm_prepare()
538 azx_setup_controller(chip, azx_dev); in azx_pcm_prepare()
541 azx_sd_readw(chip, azx_dev, SD_FIFOSIZE) + 1; in azx_pcm_prepare()
547 if ((chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND) && in azx_pcm_prepare()
548 stream_tag > chip->capture_streams) in azx_pcm_prepare()
549 stream_tag -= chip->capture_streams; in azx_pcm_prepare()
563 struct azx *chip = apcm->chip; in azx_pcm_trigger() local
570 trace_azx_pcm_trigger(chip, azx_dev, cmd); in azx_pcm_trigger()
600 spin_lock(&chip->reg_lock); in azx_pcm_trigger()
603 if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC) in azx_pcm_trigger()
604 azx_writel(chip, OLD_SSYNC, in azx_pcm_trigger()
605 azx_readl(chip, OLD_SSYNC) | sbits); in azx_pcm_trigger()
607 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) | sbits); in azx_pcm_trigger()
614 azx_dev->start_wallclk = azx_readl(chip, WALLCLK); in azx_pcm_trigger()
618 azx_stream_start(chip, azx_dev); in azx_pcm_trigger()
620 azx_stream_stop(chip, azx_dev); in azx_pcm_trigger()
624 spin_unlock(&chip->reg_lock); in azx_pcm_trigger()
633 if (!(azx_sd_readb(chip, azx_dev, SD_STS) & in azx_pcm_trigger()
649 if (azx_sd_readb(chip, azx_dev, SD_CTL) & in azx_pcm_trigger()
658 spin_lock(&chip->reg_lock); in azx_pcm_trigger()
660 if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC) in azx_pcm_trigger()
661 azx_writel(chip, OLD_SSYNC, in azx_pcm_trigger()
662 azx_readl(chip, OLD_SSYNC) & ~sbits); in azx_pcm_trigger()
664 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) & ~sbits); in azx_pcm_trigger()
684 spin_unlock(&chip->reg_lock); in azx_pcm_trigger()
688 unsigned int azx_get_pos_lpib(struct azx *chip, struct azx_dev *azx_dev) in azx_get_pos_lpib() argument
690 return azx_sd_readl(chip, azx_dev, SD_LPIB); in azx_get_pos_lpib()
694 unsigned int azx_get_pos_posbuf(struct azx *chip, struct azx_dev *azx_dev) in azx_get_pos_posbuf() argument
700 unsigned int azx_get_position(struct azx *chip, in azx_get_position() argument
708 if (chip->get_position[stream]) in azx_get_position()
709 pos = chip->get_position[stream](chip, azx_dev); in azx_get_position()
711 pos = azx_get_pos_posbuf(chip, azx_dev); in azx_get_position()
720 if (chip->get_delay[stream]) in azx_get_position()
721 delay += chip->get_delay[stream](chip, azx_dev, pos); in azx_get_position()
728 trace_azx_get_position(chip, azx_dev, pos, delay); in azx_get_position()
736 struct azx *chip = apcm->chip; in azx_pcm_pointer() local
739 azx_get_position(chip, azx_dev)); in azx_pcm_pointer()
802 struct azx *chip = apcm->chip; in azx_pcm_open() local
810 mutex_lock(&chip->open_mutex); in azx_pcm_open()
811 azx_dev = azx_assign_device(chip, substream); in azx_pcm_open()
829 if (chip->align_buffer_size) in azx_pcm_open()
877 spin_lock_irqsave(&chip->reg_lock, flags); in azx_pcm_open()
880 spin_unlock_irqrestore(&chip->reg_lock, flags); in azx_pcm_open()
884 mutex_unlock(&chip->open_mutex); in azx_pcm_open()
890 mutex_unlock(&chip->open_mutex); in azx_pcm_open()
899 struct azx *chip = apcm->chip; in azx_pcm_mmap() local
900 if (chip->ops->pcm_mmap_prepare) in azx_pcm_mmap()
901 chip->ops->pcm_mmap_prepare(substream, area); in azx_pcm_mmap()
934 struct azx *chip = bus->private_data; in azx_attach_pcm_stream() local
941 list_for_each_entry(apcm, &chip->pcm_list, list) { in azx_attach_pcm_stream()
943 dev_err(chip->card->dev, "PCM %d already exists\n", in azx_attach_pcm_stream()
948 err = snd_pcm_new(chip->card, cpcm->name, pcm_dev, in azx_attach_pcm_stream()
958 apcm->chip = chip; in azx_attach_pcm_stream()
966 list_add_tail(&apcm->list, &chip->pcm_list); in azx_attach_pcm_stream()
977 chip->card->dev, in azx_attach_pcm_stream()
985 static int azx_alloc_cmd_io(struct azx *chip) in azx_alloc_cmd_io() argument
988 return chip->ops->dma_alloc_pages(chip, SNDRV_DMA_TYPE_DEV, in azx_alloc_cmd_io()
989 PAGE_SIZE, &chip->rb); in azx_alloc_cmd_io()
992 static void azx_init_cmd_io(struct azx *chip) in azx_init_cmd_io() argument
996 spin_lock_irq(&chip->reg_lock); in azx_init_cmd_io()
998 chip->corb.addr = chip->rb.addr; in azx_init_cmd_io()
999 chip->corb.buf = (u32 *)chip->rb.area; in azx_init_cmd_io()
1000 azx_writel(chip, CORBLBASE, (u32)chip->corb.addr); in azx_init_cmd_io()
1001 azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr)); in azx_init_cmd_io()
1004 azx_writeb(chip, CORBSIZE, 0x02); in azx_init_cmd_io()
1006 azx_writew(chip, CORBWP, 0); in azx_init_cmd_io()
1009 azx_writew(chip, CORBRP, AZX_CORBRP_RST); in azx_init_cmd_io()
1010 if (!(chip->driver_caps & AZX_DCAPS_CORBRP_SELF_CLEAR)) { in azx_init_cmd_io()
1012 if ((azx_readw(chip, CORBRP) & AZX_CORBRP_RST) == AZX_CORBRP_RST) in azx_init_cmd_io()
1017 dev_err(chip->card->dev, "CORB reset timeout#1, CORBRP = %d\n", in azx_init_cmd_io()
1018 azx_readw(chip, CORBRP)); in azx_init_cmd_io()
1020 azx_writew(chip, CORBRP, 0); in azx_init_cmd_io()
1022 if (azx_readw(chip, CORBRP) == 0) in azx_init_cmd_io()
1027 dev_err(chip->card->dev, "CORB reset timeout#2, CORBRP = %d\n", in azx_init_cmd_io()
1028 azx_readw(chip, CORBRP)); in azx_init_cmd_io()
1032 azx_writeb(chip, CORBCTL, AZX_CORBCTL_RUN); in azx_init_cmd_io()
1035 chip->rirb.addr = chip->rb.addr + 2048; in azx_init_cmd_io()
1036 chip->rirb.buf = (u32 *)(chip->rb.area + 2048); in azx_init_cmd_io()
1037 chip->rirb.wp = chip->rirb.rp = 0; in azx_init_cmd_io()
1038 memset(chip->rirb.cmds, 0, sizeof(chip->rirb.cmds)); in azx_init_cmd_io()
1039 azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr); in azx_init_cmd_io()
1040 azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr)); in azx_init_cmd_io()
1043 azx_writeb(chip, RIRBSIZE, 0x02); in azx_init_cmd_io()
1045 azx_writew(chip, RIRBWP, AZX_RIRBWP_RST); in azx_init_cmd_io()
1047 if (chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND) in azx_init_cmd_io()
1048 azx_writew(chip, RINTCNT, 0xc0); in azx_init_cmd_io()
1050 azx_writew(chip, RINTCNT, 1); in azx_init_cmd_io()
1052 azx_writeb(chip, RIRBCTL, AZX_RBCTL_DMA_EN | AZX_RBCTL_IRQ_EN); in azx_init_cmd_io()
1053 spin_unlock_irq(&chip->reg_lock); in azx_init_cmd_io()
1056 static void azx_free_cmd_io(struct azx *chip) in azx_free_cmd_io() argument
1058 spin_lock_irq(&chip->reg_lock); in azx_free_cmd_io()
1060 azx_writeb(chip, RIRBCTL, 0); in azx_free_cmd_io()
1061 azx_writeb(chip, CORBCTL, 0); in azx_free_cmd_io()
1062 spin_unlock_irq(&chip->reg_lock); in azx_free_cmd_io()
1080 struct azx *chip = bus->private_data; in azx_corb_send_cmd() local
1084 spin_lock_irq(&chip->reg_lock); in azx_corb_send_cmd()
1087 wp = azx_readw(chip, CORBWP); in azx_corb_send_cmd()
1090 spin_unlock_irq(&chip->reg_lock); in azx_corb_send_cmd()
1096 rp = azx_readw(chip, CORBRP); in azx_corb_send_cmd()
1099 spin_unlock_irq(&chip->reg_lock); in azx_corb_send_cmd()
1103 chip->rirb.cmds[addr]++; in azx_corb_send_cmd()
1104 chip->corb.buf[wp] = cpu_to_le32(val); in azx_corb_send_cmd()
1105 azx_writew(chip, CORBWP, wp); in azx_corb_send_cmd()
1107 spin_unlock_irq(&chip->reg_lock); in azx_corb_send_cmd()
1115 static void azx_update_rirb(struct azx *chip) in azx_update_rirb() argument
1121 wp = azx_readw(chip, RIRBWP); in azx_update_rirb()
1127 if (wp == chip->rirb.wp) in azx_update_rirb()
1129 chip->rirb.wp = wp; in azx_update_rirb()
1131 while (chip->rirb.rp != wp) { in azx_update_rirb()
1132 chip->rirb.rp++; in azx_update_rirb()
1133 chip->rirb.rp %= AZX_MAX_RIRB_ENTRIES; in azx_update_rirb()
1135 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */ in azx_update_rirb()
1136 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]); in azx_update_rirb()
1137 res = le32_to_cpu(chip->rirb.buf[rp]); in azx_update_rirb()
1139 if ((addr >= AZX_MAX_CODECS) || !(chip->codec_mask & (1 << addr))) { in azx_update_rirb()
1140 dev_err(chip->card->dev, "spurious response %#x:%#x, rp = %d, wp = %d", in azx_update_rirb()
1142 chip->rirb.rp, wp); in azx_update_rirb()
1145 snd_hda_queue_unsol_event(chip->bus, res, res_ex); in azx_update_rirb()
1146 else if (chip->rirb.cmds[addr]) { in azx_update_rirb()
1147 chip->rirb.res[addr] = res; in azx_update_rirb()
1149 chip->rirb.cmds[addr]--; in azx_update_rirb()
1151 dev_err(chip->card->dev, "spurious response %#x:%#x, last cmd=%#08x\n", in azx_update_rirb()
1153 chip->last_cmd[addr]); in azx_update_rirb()
1162 struct azx *chip = bus->private_data; in azx_rirb_get_response() local
1171 if (chip->polling_mode || do_poll) { in azx_rirb_get_response()
1172 spin_lock_irq(&chip->reg_lock); in azx_rirb_get_response()
1173 azx_update_rirb(chip); in azx_rirb_get_response()
1174 spin_unlock_irq(&chip->reg_lock); in azx_rirb_get_response()
1176 if (!chip->rirb.cmds[addr]) { in azx_rirb_get_response()
1181 chip->poll_count = 0; in azx_rirb_get_response()
1182 return chip->rirb.res[addr]; /* the last value */ in azx_rirb_get_response()
1197 if (!chip->polling_mode && chip->poll_count < 2) { in azx_rirb_get_response()
1198 dev_dbg(chip->card->dev, in azx_rirb_get_response()
1200 chip->last_cmd[addr]); in azx_rirb_get_response()
1202 chip->poll_count++; in azx_rirb_get_response()
1207 if (!chip->polling_mode) { in azx_rirb_get_response()
1208 dev_warn(chip->card->dev, in azx_rirb_get_response()
1210 chip->last_cmd[addr]); in azx_rirb_get_response()
1211 chip->polling_mode = 1; in azx_rirb_get_response()
1215 if (chip->msi) { in azx_rirb_get_response()
1216 dev_warn(chip->card->dev, in azx_rirb_get_response()
1218 chip->last_cmd[addr]); in azx_rirb_get_response()
1219 if (chip->ops->disable_msi_reset_irq(chip) && in azx_rirb_get_response()
1220 chip->ops->disable_msi_reset_irq(chip) < 0) { in azx_rirb_get_response()
1227 if (chip->probing) { in azx_rirb_get_response()
1244 dev_err(chip->card->dev, in azx_rirb_get_response()
1246 chip->last_cmd[addr]); in azx_rirb_get_response()
1247 chip->single_cmd = 1; in azx_rirb_get_response()
1250 azx_free_cmd_io(chip); in azx_rirb_get_response()
1252 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~AZX_GCTL_UNSOL); in azx_rirb_get_response()
1267 static int azx_single_wait_for_response(struct azx *chip, unsigned int addr) in azx_single_wait_for_response() argument
1273 if (azx_readw(chip, IRS) & AZX_IRS_VALID) { in azx_single_wait_for_response()
1275 chip->rirb.res[addr] = azx_readl(chip, IR); in azx_single_wait_for_response()
1281 dev_dbg(chip->card->dev, "get_response timeout: IRS=0x%x\n", in azx_single_wait_for_response()
1282 azx_readw(chip, IRS)); in azx_single_wait_for_response()
1283 chip->rirb.res[addr] = -1; in azx_single_wait_for_response()
1290 struct azx *chip = bus->private_data; in azx_single_send_cmd() local
1297 if (!((azx_readw(chip, IRS) & AZX_IRS_BUSY))) { in azx_single_send_cmd()
1299 azx_writew(chip, IRS, azx_readw(chip, IRS) | in azx_single_send_cmd()
1301 azx_writel(chip, IC, val); in azx_single_send_cmd()
1302 azx_writew(chip, IRS, azx_readw(chip, IRS) | in azx_single_send_cmd()
1304 return azx_single_wait_for_response(chip, addr); in azx_single_send_cmd()
1309 dev_dbg(chip->card->dev, in azx_single_send_cmd()
1311 azx_readw(chip, IRS), val); in azx_single_send_cmd()
1319 struct azx *chip = bus->private_data; in azx_single_get_response() local
1320 return chip->rirb.res[addr]; in azx_single_get_response()
1333 struct azx *chip = bus->private_data; in azx_send_cmd() local
1335 if (chip->disabled) in azx_send_cmd()
1337 chip->last_cmd[azx_command_addr(val)] = val; in azx_send_cmd()
1338 if (chip->single_cmd) in azx_send_cmd()
1348 struct azx *chip = bus->private_data; in azx_get_response() local
1349 if (chip->disabled) in azx_get_response()
1351 if (chip->single_cmd) in azx_get_response()
1364 azx_get_dsp_loader_dev(struct azx *chip) in azx_get_dsp_loader_dev() argument
1366 return &chip->azx_dev[chip->playback_index_offset]; in azx_get_dsp_loader_dev()
1374 struct azx *chip = bus->private_data; in azx_load_dsp_prepare() local
1378 azx_dev = azx_get_dsp_loader_dev(chip); in azx_load_dsp_prepare()
1381 spin_lock_irq(&chip->reg_lock); in azx_load_dsp_prepare()
1383 spin_unlock_irq(&chip->reg_lock); in azx_load_dsp_prepare()
1388 chip->saved_azx_dev = *azx_dev; in azx_load_dsp_prepare()
1390 spin_unlock_irq(&chip->reg_lock); in azx_load_dsp_prepare()
1392 err = chip->ops->dma_alloc_pages(chip, SNDRV_DMA_TYPE_DEV_SG, in azx_load_dsp_prepare()
1401 azx_stream_reset(chip, azx_dev); in azx_load_dsp_prepare()
1404 azx_sd_writel(chip, azx_dev, SD_BDLPL, 0); in azx_load_dsp_prepare()
1405 azx_sd_writel(chip, azx_dev, SD_BDLPU, 0); in azx_load_dsp_prepare()
1409 err = setup_bdle(chip, bufp, azx_dev, &bdl, 0, byte_size, 0); in azx_load_dsp_prepare()
1413 azx_setup_controller(chip, azx_dev); in azx_load_dsp_prepare()
1418 chip->ops->dma_free_pages(chip, bufp); in azx_load_dsp_prepare()
1420 spin_lock_irq(&chip->reg_lock); in azx_load_dsp_prepare()
1422 *azx_dev = chip->saved_azx_dev; in azx_load_dsp_prepare()
1424 spin_unlock_irq(&chip->reg_lock); in azx_load_dsp_prepare()
1432 struct azx *chip = bus->private_data; in azx_load_dsp_trigger() local
1433 struct azx_dev *azx_dev = azx_get_dsp_loader_dev(chip); in azx_load_dsp_trigger()
1436 azx_stream_start(chip, azx_dev); in azx_load_dsp_trigger()
1438 azx_stream_stop(chip, azx_dev); in azx_load_dsp_trigger()
1445 struct azx *chip = bus->private_data; in azx_load_dsp_cleanup() local
1446 struct azx_dev *azx_dev = azx_get_dsp_loader_dev(chip); in azx_load_dsp_cleanup()
1453 azx_sd_writel(chip, azx_dev, SD_BDLPL, 0); in azx_load_dsp_cleanup()
1454 azx_sd_writel(chip, azx_dev, SD_BDLPU, 0); in azx_load_dsp_cleanup()
1455 azx_sd_writel(chip, azx_dev, SD_CTL, 0); in azx_load_dsp_cleanup()
1460 chip->ops->dma_free_pages(chip, dmab); in azx_load_dsp_cleanup()
1463 spin_lock_irq(&chip->reg_lock); in azx_load_dsp_cleanup()
1465 *azx_dev = chip->saved_azx_dev; in azx_load_dsp_cleanup()
1467 spin_unlock_irq(&chip->reg_lock); in azx_load_dsp_cleanup()
1472 int azx_alloc_stream_pages(struct azx *chip) in azx_alloc_stream_pages() argument
1476 for (i = 0; i < chip->num_streams; i++) { in azx_alloc_stream_pages()
1477 dsp_lock_init(&chip->azx_dev[i]); in azx_alloc_stream_pages()
1479 err = chip->ops->dma_alloc_pages(chip, SNDRV_DMA_TYPE_DEV, in azx_alloc_stream_pages()
1481 &chip->azx_dev[i].bdl); in azx_alloc_stream_pages()
1486 err = chip->ops->dma_alloc_pages(chip, SNDRV_DMA_TYPE_DEV, in azx_alloc_stream_pages()
1487 chip->num_streams * 8, &chip->posbuf); in azx_alloc_stream_pages()
1492 err = azx_alloc_cmd_io(chip); in azx_alloc_stream_pages()
1499 void azx_free_stream_pages(struct azx *chip) in azx_free_stream_pages() argument
1502 if (chip->azx_dev) { in azx_free_stream_pages()
1503 for (i = 0; i < chip->num_streams; i++) in azx_free_stream_pages()
1504 if (chip->azx_dev[i].bdl.area) in azx_free_stream_pages()
1505 chip->ops->dma_free_pages( in azx_free_stream_pages()
1506 chip, &chip->azx_dev[i].bdl); in azx_free_stream_pages()
1508 if (chip->rb.area) in azx_free_stream_pages()
1509 chip->ops->dma_free_pages(chip, &chip->rb); in azx_free_stream_pages()
1510 if (chip->posbuf.area) in azx_free_stream_pages()
1511 chip->ops->dma_free_pages(chip, &chip->posbuf); in azx_free_stream_pages()
1520 void azx_enter_link_reset(struct azx *chip) in azx_enter_link_reset() argument
1525 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~AZX_GCTL_RESET); in azx_enter_link_reset()
1528 while ((azx_readb(chip, GCTL) & AZX_GCTL_RESET) && in azx_enter_link_reset()
1535 static void azx_exit_link_reset(struct azx *chip) in azx_exit_link_reset() argument
1539 azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | AZX_GCTL_RESET); in azx_exit_link_reset()
1542 while (!azx_readb(chip, GCTL) && in azx_exit_link_reset()
1548 static int azx_reset(struct azx *chip, bool full_reset) in azx_reset() argument
1554 azx_writew(chip, STATESTS, STATESTS_INT_MASK); in azx_reset()
1557 azx_enter_link_reset(chip); in azx_reset()
1565 azx_exit_link_reset(chip); in azx_reset()
1572 if (!azx_readb(chip, GCTL)) { in azx_reset()
1573 dev_dbg(chip->card->dev, "azx_reset: controller not ready!\n"); in azx_reset()
1578 if (!chip->single_cmd) in azx_reset()
1579 azx_writel(chip, GCTL, azx_readl(chip, GCTL) | in azx_reset()
1583 if (!chip->codec_mask) { in azx_reset()
1584 chip->codec_mask = azx_readw(chip, STATESTS); in azx_reset()
1585 dev_dbg(chip->card->dev, "codec_mask = 0x%x\n", in azx_reset()
1586 chip->codec_mask); in azx_reset()
1593 static void azx_int_enable(struct azx *chip) in azx_int_enable() argument
1596 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) | in azx_int_enable()
1601 static void azx_int_disable(struct azx *chip) in azx_int_disable() argument
1606 for (i = 0; i < chip->num_streams; i++) { in azx_int_disable()
1607 struct azx_dev *azx_dev = &chip->azx_dev[i]; in azx_int_disable()
1608 azx_sd_writeb(chip, azx_dev, SD_CTL, in azx_int_disable()
1609 azx_sd_readb(chip, azx_dev, SD_CTL) & in azx_int_disable()
1614 azx_writeb(chip, INTCTL, 0); in azx_int_disable()
1617 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) & in azx_int_disable()
1622 static void azx_int_clear(struct azx *chip) in azx_int_clear() argument
1627 for (i = 0; i < chip->num_streams; i++) { in azx_int_clear()
1628 struct azx_dev *azx_dev = &chip->azx_dev[i]; in azx_int_clear()
1629 azx_sd_writeb(chip, azx_dev, SD_STS, SD_INT_MASK); in azx_int_clear()
1633 azx_writew(chip, STATESTS, STATESTS_INT_MASK); in azx_int_clear()
1636 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK); in azx_int_clear()
1639 azx_writel(chip, INTSTS, AZX_INT_CTRL_EN | AZX_INT_ALL_STREAM); in azx_int_clear()
1645 void azx_init_chip(struct azx *chip, bool full_reset) in azx_init_chip() argument
1647 if (chip->initialized) in azx_init_chip()
1651 azx_reset(chip, full_reset); in azx_init_chip()
1654 azx_int_clear(chip); in azx_init_chip()
1655 azx_int_enable(chip); in azx_init_chip()
1658 if (!chip->single_cmd) in azx_init_chip()
1659 azx_init_cmd_io(chip); in azx_init_chip()
1662 azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr); in azx_init_chip()
1663 azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr)); in azx_init_chip()
1665 chip->initialized = 1; in azx_init_chip()
1669 void azx_stop_chip(struct azx *chip) in azx_stop_chip() argument
1671 if (!chip->initialized) in azx_stop_chip()
1675 azx_int_disable(chip); in azx_stop_chip()
1676 azx_int_clear(chip); in azx_stop_chip()
1679 azx_free_cmd_io(chip); in azx_stop_chip()
1682 azx_writel(chip, DPLBASE, 0); in azx_stop_chip()
1683 azx_writel(chip, DPUBASE, 0); in azx_stop_chip()
1685 chip->initialized = 0; in azx_stop_chip()
1694 struct azx *chip = dev_id; in azx_interrupt() local
1701 if (azx_has_pm_runtime(chip)) in azx_interrupt()
1702 if (!pm_runtime_active(chip->card->dev)) in azx_interrupt()
1706 spin_lock(&chip->reg_lock); in azx_interrupt()
1708 if (chip->disabled) { in azx_interrupt()
1709 spin_unlock(&chip->reg_lock); in azx_interrupt()
1713 status = azx_readl(chip, INTSTS); in azx_interrupt()
1715 spin_unlock(&chip->reg_lock); in azx_interrupt()
1719 for (i = 0; i < chip->num_streams; i++) { in azx_interrupt()
1720 azx_dev = &chip->azx_dev[i]; in azx_interrupt()
1722 sd_status = azx_sd_readb(chip, azx_dev, SD_STS); in azx_interrupt()
1723 azx_sd_writeb(chip, azx_dev, SD_STS, SD_INT_MASK); in azx_interrupt()
1728 if (!chip->ops->position_check || in azx_interrupt()
1729 chip->ops->position_check(chip, azx_dev)) { in azx_interrupt()
1730 spin_unlock(&chip->reg_lock); in azx_interrupt()
1732 spin_lock(&chip->reg_lock); in azx_interrupt()
1738 status = azx_readb(chip, RIRBSTS); in azx_interrupt()
1741 if (chip->driver_caps & AZX_DCAPS_RIRB_PRE_DELAY) in azx_interrupt()
1743 azx_update_rirb(chip); in azx_interrupt()
1745 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK); in azx_interrupt()
1748 spin_unlock(&chip->reg_lock); in azx_interrupt()
1761 static int probe_codec(struct azx *chip, int addr) in probe_codec() argument
1767 mutex_lock(&chip->bus->core.cmd_mutex); in probe_codec()
1768 chip->probing = 1; in probe_codec()
1769 azx_send_cmd(chip->bus, cmd); in probe_codec()
1770 res = azx_get_response(chip->bus, addr); in probe_codec()
1771 chip->probing = 0; in probe_codec()
1772 mutex_unlock(&chip->bus->core.cmd_mutex); in probe_codec()
1775 dev_dbg(chip->card->dev, "codec #%d probed OK\n", addr); in probe_codec()
1781 struct azx *chip = bus->private_data; in azx_bus_reset() local
1784 azx_stop_chip(chip); in azx_bus_reset()
1785 azx_init_chip(chip, true); in azx_bus_reset()
1786 if (chip->initialized) in azx_bus_reset()
1787 snd_hda_bus_reset(chip->bus); in azx_bus_reset()
1791 static int get_jackpoll_interval(struct azx *chip) in get_jackpoll_interval() argument
1796 if (!chip->jackpoll_ms) in get_jackpoll_interval()
1799 i = chip->jackpoll_ms[chip->dev_index]; in get_jackpoll_interval()
1807 dev_warn(chip->card->dev, in get_jackpoll_interval()
1825 int azx_bus_create(struct azx *chip, const char *model) in azx_bus_create() argument
1830 err = snd_hda_bus_new(chip->card, &bus); in azx_bus_create()
1834 chip->bus = bus; in azx_bus_create()
1835 bus->private_data = chip; in azx_bus_create()
1836 bus->pci = chip->pci; in azx_bus_create()
1840 if (chip->driver_caps & AZX_DCAPS_RIRB_DELAY) { in azx_bus_create()
1841 dev_dbg(chip->card->dev, "Enable delay in RIRB handling\n"); in azx_bus_create()
1849 if (chip->driver_caps & AZX_DCAPS_SYNC_WRITE) { in azx_bus_create()
1850 dev_dbg(chip->card->dev, "Enable sync_write for stable communication\n"); in azx_bus_create()
1860 int azx_probe_codecs(struct azx *chip, unsigned int max_slots) in azx_probe_codecs() argument
1862 struct hda_bus *bus = chip->bus; in azx_probe_codecs()
1871 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) { in azx_probe_codecs()
1872 if (probe_codec(chip, c) < 0) { in azx_probe_codecs()
1876 dev_warn(chip->card->dev, in azx_probe_codecs()
1878 chip->codec_mask &= ~(1 << c); in azx_probe_codecs()
1886 azx_stop_chip(chip); in azx_probe_codecs()
1887 azx_init_chip(chip, true); in azx_probe_codecs()
1894 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) { in azx_probe_codecs()
1899 codec->jackpoll_interval = get_jackpoll_interval(chip); in azx_probe_codecs()
1900 codec->beep_mode = chip->beep_mode; in azx_probe_codecs()
1905 dev_err(chip->card->dev, "no codecs initialized\n"); in azx_probe_codecs()
1913 int azx_codec_configure(struct azx *chip) in azx_codec_configure() argument
1916 list_for_each_codec(codec, chip->bus) { in azx_codec_configure()
1924 static bool is_input_stream(struct azx *chip, unsigned char index) in is_input_stream() argument
1926 return (index >= chip->capture_index_offset && in is_input_stream()
1927 index < chip->capture_index_offset + chip->capture_streams); in is_input_stream()
1931 int azx_init_stream(struct azx *chip) in azx_init_stream() argument
1941 for (i = 0; i < chip->num_streams; i++) { in azx_init_stream()
1942 struct azx_dev *azx_dev = &chip->azx_dev[i]; in azx_init_stream()
1943 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8); in azx_init_stream()
1945 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80); in azx_init_stream()
1956 if (chip->driver_caps & AZX_DCAPS_SEPARATE_STREAM_TAG) in azx_init_stream()
1958 is_input_stream(chip, i) ? in azx_init_stream()