Lines Matching refs:chip
36 static int check_asic_status(struct echoaudio *chip) in check_asic_status() argument
40 if (wait_handshake(chip)) in check_asic_status()
43 chip->comm_page->ext_box_status = cpu_to_le32(E3G_ASIC_NOT_LOADED); in check_asic_status()
44 chip->asic_loaded = FALSE; in check_asic_status()
45 clear_handshake(chip); in check_asic_status()
46 send_vector(chip, DSP_VC_TEST_ASIC); in check_asic_status()
48 if (wait_handshake(chip)) { in check_asic_status()
49 chip->dsp_code = NULL; in check_asic_status()
53 box_status = le32_to_cpu(chip->comm_page->ext_box_status); in check_asic_status()
54 dev_dbg(chip->card->dev, "box_status=%x\n", box_status); in check_asic_status()
58 chip->asic_loaded = TRUE; in check_asic_status()
64 static inline u32 get_frq_reg(struct echoaudio *chip) in get_frq_reg() argument
66 return le32_to_cpu(chip->comm_page->e3g_frq_register); in get_frq_reg()
73 static int write_control_reg(struct echoaudio *chip, u32 ctl, u32 frq, in write_control_reg() argument
76 if (wait_handshake(chip)) in write_control_reg()
79 dev_dbg(chip->card->dev, in write_control_reg()
85 if (ctl != chip->comm_page->control_register || in write_control_reg()
86 frq != chip->comm_page->e3g_frq_register || force) { in write_control_reg()
87 chip->comm_page->e3g_frq_register = frq; in write_control_reg()
88 chip->comm_page->control_register = ctl; in write_control_reg()
89 clear_handshake(chip); in write_control_reg()
90 return send_vector(chip, DSP_VC_WRITE_CONTROL_REG); in write_control_reg()
93 dev_dbg(chip->card->dev, "WriteControlReg: not written, no change\n"); in write_control_reg()
100 static int set_digital_mode(struct echoaudio *chip, u8 mode) in set_digital_mode() argument
106 if (snd_BUG_ON(chip->pipe_alloc_mask)) in set_digital_mode()
109 if (snd_BUG_ON(!(chip->digital_modes & (1 << mode)))) in set_digital_mode()
112 previous_mode = chip->digital_mode; in set_digital_mode()
113 err = dsp_set_digital_mode(chip, mode); in set_digital_mode()
120 spin_lock_irq(&chip->lock); in set_digital_mode()
121 for (o = 0; o < num_busses_out(chip); o++) in set_digital_mode()
122 for (i = 0; i < num_busses_in(chip); i++) in set_digital_mode()
123 set_monitor_gain(chip, o, i, in set_digital_mode()
124 chip->monitor_gain[o][i]); in set_digital_mode()
127 for (i = 0; i < num_busses_in(chip); i++) in set_digital_mode()
128 set_input_gain(chip, i, chip->input_gain[i]); in set_digital_mode()
129 update_input_line_level(chip); in set_digital_mode()
132 for (o = 0; o < num_busses_out(chip); o++) in set_digital_mode()
133 set_output_gain(chip, o, chip->output_gain[o]); in set_digital_mode()
134 update_output_line_level(chip); in set_digital_mode()
135 spin_unlock_irq(&chip->lock); in set_digital_mode()
143 static u32 set_spdif_bits(struct echoaudio *chip, u32 control_reg, u32 rate) in set_spdif_bits() argument
152 if (chip->professional_spdif) in set_spdif_bits()
160 if (chip->professional_spdif) in set_spdif_bits()
163 if (chip->non_audio_spdif) in set_spdif_bits()
175 static int set_professional_spdif(struct echoaudio *chip, char prof) in set_professional_spdif() argument
179 control_reg = le32_to_cpu(chip->comm_page->control_register); in set_professional_spdif()
180 chip->professional_spdif = prof; in set_professional_spdif()
181 control_reg = set_spdif_bits(chip, control_reg, chip->sample_rate); in set_professional_spdif()
182 return write_control_reg(chip, control_reg, get_frq_reg(chip), 0); in set_professional_spdif()
191 static u32 detect_input_clocks(const struct echoaudio *chip) in detect_input_clocks() argument
197 clocks_from_dsp = le32_to_cpu(chip->comm_page->status_clocks); in detect_input_clocks()
204 switch(chip->digital_mode) { in detect_input_clocks()
221 static int load_asic(struct echoaudio *chip) in load_asic() argument
225 if (chip->asic_loaded) in load_asic()
231 err = load_asic_generic(chip, DSP_FNC_LOAD_3G_ASIC, FW_3G_ASIC); in load_asic()
235 chip->asic_code = FW_3G_ASIC; in load_asic()
240 box_type = check_asic_status(chip); in load_asic()
245 err = write_control_reg(chip, E3G_48KHZ, in load_asic()
256 static int set_sample_rate(struct echoaudio *chip, u32 rate) in set_sample_rate() argument
261 if (chip->input_clock != ECHO_CLOCK_INTERNAL) { in set_sample_rate()
262 dev_warn(chip->card->dev, in set_sample_rate()
265 chip->comm_page->sample_rate = cpu_to_le32(rate); in set_sample_rate()
266 chip->sample_rate = rate; in set_sample_rate()
267 set_input_clock(chip, chip->input_clock); in set_sample_rate()
272 chip->digital_mode == DIGITAL_MODE_ADAT)) in set_sample_rate()
276 control_reg = le32_to_cpu(chip->comm_page->control_register); in set_sample_rate()
303 control_reg = set_spdif_bits(chip, control_reg, rate); in set_sample_rate()
315 chip->comm_page->sample_rate = cpu_to_le32(rate); /* ignored by the DSP */ in set_sample_rate()
316 chip->sample_rate = rate; in set_sample_rate()
317 dev_dbg(chip->card->dev, in set_sample_rate()
321 return write_control_reg(chip, control_reg, frq_reg, 0); in set_sample_rate()
327 static int set_input_clock(struct echoaudio *chip, u16 clock) in set_input_clock() argument
333 control_reg = le32_to_cpu(chip->comm_page->control_register) & in set_input_clock()
335 clocks_from_dsp = le32_to_cpu(chip->comm_page->status_clocks); in set_input_clock()
339 chip->input_clock = ECHO_CLOCK_INTERNAL; in set_input_clock()
340 return set_sample_rate(chip, chip->sample_rate); in set_input_clock()
342 if (chip->digital_mode == DIGITAL_MODE_ADAT) in set_input_clock()
351 if (chip->digital_mode != DIGITAL_MODE_ADAT) in set_input_clock()
364 dev_err(chip->card->dev, in set_input_clock()
369 chip->input_clock = clock; in set_input_clock()
370 return write_control_reg(chip, control_reg, get_frq_reg(chip), 1); in set_input_clock()
375 static int dsp_set_digital_mode(struct echoaudio *chip, u8 mode) in dsp_set_digital_mode() argument
385 if (chip->input_clock == ECHO_CLOCK_ADAT) in dsp_set_digital_mode()
389 if (chip->input_clock == ECHO_CLOCK_SPDIF) in dsp_set_digital_mode()
393 dev_err(chip->card->dev, in dsp_set_digital_mode()
398 spin_lock_irq(&chip->lock); in dsp_set_digital_mode()
401 chip->sample_rate = 48000; in dsp_set_digital_mode()
402 set_input_clock(chip, ECHO_CLOCK_INTERNAL); in dsp_set_digital_mode()
406 control_reg = le32_to_cpu(chip->comm_page->control_register); in dsp_set_digital_mode()
423 err = write_control_reg(chip, control_reg, get_frq_reg(chip), 1); in dsp_set_digital_mode()
424 spin_unlock_irq(&chip->lock); in dsp_set_digital_mode()
427 chip->digital_mode = mode; in dsp_set_digital_mode()
429 dev_dbg(chip->card->dev, "set_digital_mode(%d)\n", chip->digital_mode); in dsp_set_digital_mode()