582         __raw_writeq(M_SYNCSER_CMD_RX_RESET | M_SYNCSER_CMD_TX_RESET, SS_CSR(R_SER_CMD));  in ser_init()
584         __raw_writeq(M_SYNCSER_MSB_FIRST, SS_CSR(R_SER_MODE));  in ser_init()
585         __raw_writeq(32, SS_CSR(R_SER_MINFRM_SZ));  in ser_init()
586         __raw_writeq(32, SS_CSR(R_SER_MAXFRM_SZ));  in ser_init()
588         __raw_writeq(1, SS_CSR(R_SER_TX_RD_THRSH));  in ser_init()
589         __raw_writeq(4, SS_CSR(R_SER_TX_WR_THRSH));  in ser_init()
590         __raw_writeq(8, SS_CSR(R_SER_RX_RD_THRSH));  in ser_init()
593         __raw_writeq((M_SYNCSER_TXSYNC_INT | V_SYNCSER_TXSYNC_DLY(0) | M_SYNCSER_TXCLK_EXT |  in ser_init()
598         __raw_writeq(V_SYNCSER_SEQ_COUNT(14) | M_SYNCSER_SEQ_ENABLE | M_SYNCSER_SEQ_STROBE,  in ser_init()
600         __raw_writeq(V_SYNCSER_SEQ_COUNT(15) | M_SYNCSER_SEQ_ENABLE | M_SYNCSER_SEQ_BYTE,  in ser_init()
602         __raw_writeq(V_SYNCSER_SEQ_COUNT(13) | M_SYNCSER_SEQ_ENABLE | M_SYNCSER_SEQ_BYTE,  in ser_init()
604         __raw_writeq(V_SYNCSER_SEQ_COUNT( 0) | M_SYNCSER_SEQ_ENABLE |  in ser_init()
607         __raw_writeq(V_SYNCSER_SEQ_COUNT(14) | M_SYNCSER_SEQ_ENABLE | M_SYNCSER_SEQ_STROBE,  in ser_init()
609         __raw_writeq(V_SYNCSER_SEQ_COUNT(15) | M_SYNCSER_SEQ_ENABLE | M_SYNCSER_SEQ_BYTE,  in ser_init()
611         __raw_writeq(V_SYNCSER_SEQ_COUNT(13) | M_SYNCSER_SEQ_ENABLE | M_SYNCSER_SEQ_BYTE,  in ser_init()
613         __raw_writeq(V_SYNCSER_SEQ_COUNT( 0) | M_SYNCSER_SEQ_ENABLE | M_SYNCSER_SEQ_STROBE |  in ser_init()
618                 __raw_writeq(M_SYNCSER_SEQ_LAST, SS_TXTBL(i));  in ser_init()
619                 __raw_writeq(M_SYNCSER_SEQ_LAST, SS_RXTBL(i));  in ser_init()
700         __raw_writeq((M_DMA_EOP_INT_EN | V_DMA_INT_PKTCNT(DMA_INT_CNT) |  in dma_init()
703         __raw_writeq(M_DMA_L2CA, SS_CSR(R_SER_DMA_CONFIG1_RX));  in dma_init()
704         __raw_writeq(s->dma_adc.descrtab_phys, SS_CSR(R_SER_DMA_DSCR_BASE_RX));  in dma_init()
706         __raw_writeq(V_DMA_RINGSZ(DMA_DESCR), SS_CSR(R_SER_DMA_CONFIG0_TX));  in dma_init()
707         __raw_writeq(M_DMA_L2CA | M_DMA_NO_DSCR_UPDT, SS_CSR(R_SER_DMA_CONFIG1_TX));  in dma_init()
708         __raw_writeq(s->dma_dac.descrtab_phys, SS_CSR(R_SER_DMA_DSCR_BASE_TX));  in dma_init()
711         __raw_writeq(DMA_DESCR, SS_CSR(R_SER_DMA_DSCR_COUNT_RX));  in dma_init()
713         __raw_writeq(M_SYNCSER_DMA_RX_EN | M_SYNCSER_DMA_TX_EN, SS_CSR(R_SER_DMA_ENABLE));  in dma_init()
715         __raw_writeq((M_SYNCSER_RX_SYNC_ERR | M_SYNCSER_RX_OVERRUN | M_SYNCSER_RX_EOP_COUNT),  in dma_init()
721         __raw_writeq(M_SYNCSER_CMD_TX_EN, SS_CSR(R_SER_CMD));  in dma_init()
723         __raw_writeq(M_SYNCSER_CMD_RX_EN | M_SYNCSER_CMD_TX_EN, SS_CSR(R_SER_CMD));  in dma_init()
772                 __raw_writeq(1, SS_CSR(R_SER_DMA_DSCR_COUNT_TX));  in serdma_reg_access()
826         __raw_writeq((s->ena & FMODE_READ) ? M_SYNCSER_DMA_RX_EN : 0,  in stop_dac()
1011                         __raw_writeq(diff, SS_CSR(R_SER_DMA_DSCR_COUNT_RX));  in cs4297a_update_ptr()
1067                                 __raw_writeq(1, SS_CSR(R_SER_DMA_DSCR_COUNT_RX));  in cs4297a_update_ptr()
1888                 __raw_writeq(cnt/FRAME_SAMPLE_BYTES, SS_CSR(R_SER_DMA_DSCR_COUNT_TX));  in cs4297a_write()
2593                 __raw_writeq(DMA_DESCR, SS_CSR(R_SER_DMA_DSCR_COUNT_RX));  in cs4297a_interrupt()
2640                 __raw_writeq(cfg | M_SYS_SER1_ENABLE, KSEG1+A_SCD_SYSTEM_CFG);  in cs4297a_init()
2651                 __raw_writeq(mdio_val, KSEG1+A_MAC_REGISTER(2, R_MAC_MDIO));  in cs4297a_init()
2656         __raw_writeq(mdio_val | M_MAC_GENC, KSEG1+A_MAC_REGISTER(2, R_MAC_MDIO));  in cs4297a_init()