180 	     timeout > 0 && (wss_inb(chip, CS4231P(REGSEL)) & CS4231_INIT);  in snd_wss_wait()
191 	     timeout > 0 && (wss_inb(chip, CS4231P(REGSEL)) & CS4231_INIT);  in snd_wss_dout()
194 	wss_outb(chip, CS4231P(REGSEL), chip->mce_bit | reg);  in snd_wss_dout()
195 	wss_outb(chip, CS4231P(REG), value);  in snd_wss_dout()
203 	if (wss_inb(chip, CS4231P(REGSEL)) & CS4231_INIT)  in snd_wss_out()
207 	wss_outb(chip, CS4231P(REGSEL), chip->mce_bit | reg);  in snd_wss_out()
208 	wss_outb(chip, CS4231P(REG), value);  in snd_wss_out()
220 	if (wss_inb(chip, CS4231P(REGSEL)) & CS4231_INIT)  in snd_wss_in()
224 	wss_outb(chip, CS4231P(REGSEL), chip->mce_bit | reg);  in snd_wss_in()
226 	return wss_inb(chip, CS4231P(REG));  in snd_wss_in()
233 	wss_outb(chip, CS4231P(REGSEL), chip->mce_bit | 0x17);  in snd_cs4236_ext_out()
234 	wss_outb(chip, CS4231P(REG),  in snd_cs4236_ext_out()
236 	wss_outb(chip, CS4231P(REG), val);  in snd_cs4236_ext_out()
246 	wss_outb(chip, CS4231P(REGSEL), chip->mce_bit | 0x17);  in snd_cs4236_ext_in()
247 	wss_outb(chip, CS4231P(REG),  in snd_cs4236_ext_in()
250 	return wss_inb(chip, CS4231P(REG));  in snd_cs4236_ext_in()
254 		res = wss_inb(chip, CS4231P(REG));  in snd_cs4236_ext_in()
270 					wss_inb(chip, CS4231P(REGSEL)),
271 					wss_inb(chip, CS4231P(STATUS)));
366 		wss_inb(chip, CS4231P(REGSEL));  in snd_wss_busy_wait()
369 	     timeout > 0 && (wss_inb(chip, CS4231P(REGSEL)) & CS4231_INIT);  in snd_wss_busy_wait()
381 	if (wss_inb(chip, CS4231P(REGSEL)) & CS4231_INIT)  in snd_wss_mce_up()
387 	timeout = wss_inb(chip, CS4231P(REGSEL));  in snd_wss_mce_up()
393 		wss_outb(chip, CS4231P(REGSEL),  in snd_wss_mce_up()
409 	if (wss_inb(chip, CS4231P(REGSEL)) & CS4231_INIT)  in snd_wss_mce_down()
412 			   (long)CS4231P(REGSEL));  in snd_wss_mce_down()
416 	timeout = wss_inb(chip, CS4231P(REGSEL));  in snd_wss_mce_down()
417 	wss_outb(chip, CS4231P(REGSEL), chip->mce_bit | (timeout & 0x1f));  in snd_wss_mce_down()
452 	while (wss_inb(chip, CS4231P(REGSEL)) & CS4231_INIT) {  in snd_wss_mce_down()
461 	snd_printd("mce_down - exit = 0x%x\n", wss_inb(chip, CS4231P(REGSEL)));  in snd_wss_mce_down()
896 	wss_outb(chip, CS4231P(STATUS), 0);	/* clear IRQ */  in snd_wss_open()
897 	wss_outb(chip, CS4231P(STATUS), 0);	/* clear IRQ */  in snd_wss_open()
928 	wss_outb(chip, CS4231P(STATUS), 0);	/* clear IRQ */  in snd_wss_close()
929 	wss_outb(chip, CS4231P(STATUS), 0);	/* clear IRQ */  in snd_wss_close()
952 	wss_outb(chip, CS4231P(STATUS), 0);	/* clear IRQ */  in snd_wss_close()
953 	wss_outb(chip, CS4231P(STATUS), 0);	/* clear IRQ */  in snd_wss_close()
1146 		wss_outb(chip, CS4231P(STATUS), 0);  in snd_wss_interrupt()
1189 	while (wss_inb(chip, CS4231P(REGSEL)) & CS4231_INIT) {  in snd_ad1848_probe()
1219 	wss_inb(chip, CS4231P(STATUS));  in snd_ad1848_probe()
1220 	wss_outb(chip, CS4231P(STATUS), 0);  in snd_ad1848_probe()
1277 			if (wss_inb(chip, CS4231P(REGSEL)) & CS4231_INIT)  in snd_wss_probe()
1319 	wss_inb(chip, CS4231P(STATUS));	/* clear any pendings IRQ */  in snd_wss_probe()
1320 	wss_outb(chip, CS4231P(STATUS), 0);  in snd_wss_probe()
1674 	timeout = wss_inb(chip, CS4231P(REGSEL));  in snd_wss_resume()
1675 	wss_outb(chip, CS4231P(REGSEL), chip->mce_bit | (timeout & 0x1f));  in snd_wss_resume()