Lines Matching refs:V4L2_INIT_BT_TIMINGS
29 #define V4L2_INIT_BT_TIMINGS(_width, args...) \ macro
32 #define V4L2_INIT_BT_TIMINGS(_width, args...) \ macro
40 V4L2_INIT_BT_TIMINGS(640, 480, 0, 0, \
49 V4L2_INIT_BT_TIMINGS(720, 480, 1, 0, \
57 V4L2_INIT_BT_TIMINGS(720, 480, 0, 0, \
66 V4L2_INIT_BT_TIMINGS(720, 576, 1, 0, \
74 V4L2_INIT_BT_TIMINGS(720, 576, 0, 0, \
81 V4L2_INIT_BT_TIMINGS(1280, 720, 0, \
90 V4L2_INIT_BT_TIMINGS(1280, 720, 0, \
98 V4L2_INIT_BT_TIMINGS(1280, 720, 0, \
107 V4L2_INIT_BT_TIMINGS(1280, 720, 0, \
115 V4L2_INIT_BT_TIMINGS(1280, 720, 0, \
124 V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \
133 V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \
141 V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \
150 V4L2_INIT_BT_TIMINGS(1920, 1080, 1, \
159 V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \
167 V4L2_INIT_BT_TIMINGS(1920, 1080, 1, \
177 V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \
186 V4L2_INIT_BT_TIMINGS(3840, 2160, 0, \
195 V4L2_INIT_BT_TIMINGS(3840, 2160, 0, \
203 V4L2_INIT_BT_TIMINGS(3840, 2160, 0, \
212 V4L2_INIT_BT_TIMINGS(3840, 2160, 0, \
220 V4L2_INIT_BT_TIMINGS(3840, 2160, 0, \
229 V4L2_INIT_BT_TIMINGS(4096, 2160, 0, \
238 V4L2_INIT_BT_TIMINGS(4096, 2160, 0, \
246 V4L2_INIT_BT_TIMINGS(4096, 2160, 0, \
255 V4L2_INIT_BT_TIMINGS(4096, 2160, 0, \
263 V4L2_INIT_BT_TIMINGS(4096, 2160, 0, \
275 V4L2_INIT_BT_TIMINGS(640, 350, 0, V4L2_DV_HSYNC_POS_POL, \
282 V4L2_INIT_BT_TIMINGS(640, 400, 0, V4L2_DV_VSYNC_POS_POL, \
289 V4L2_INIT_BT_TIMINGS(720, 400, 0, V4L2_DV_VSYNC_POS_POL, \
299 V4L2_INIT_BT_TIMINGS(640, 480, 0, 0, \
306 V4L2_INIT_BT_TIMINGS(640, 480, 0, 0, \
313 V4L2_INIT_BT_TIMINGS(640, 480, 0, 0, \
321 V4L2_INIT_BT_TIMINGS(800, 600, 0, \
329 V4L2_INIT_BT_TIMINGS(800, 600, 0, \
337 V4L2_INIT_BT_TIMINGS(800, 600, 0, \
345 V4L2_INIT_BT_TIMINGS(800, 600, 0, \
353 V4L2_INIT_BT_TIMINGS(800, 600, 0, \
361 V4L2_INIT_BT_TIMINGS(800, 600, 0, V4L2_DV_HSYNC_POS_POL, \
369 V4L2_INIT_BT_TIMINGS(848, 480, 0, \
377 V4L2_INIT_BT_TIMINGS(1024, 768, 1, \
386 V4L2_INIT_BT_TIMINGS(1024, 768, 0, 0, \
393 V4L2_INIT_BT_TIMINGS(1024, 768, 0, 0, \
400 V4L2_INIT_BT_TIMINGS(1024, 768, 0, \
408 V4L2_INIT_BT_TIMINGS(1024, 768, 0, \
416 V4L2_INIT_BT_TIMINGS(1024, 768, 0, V4L2_DV_HSYNC_POS_POL, \
425 V4L2_INIT_BT_TIMINGS(1152, 864, 0, \
436 V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_HSYNC_POS_POL, \
444 V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_VSYNC_POS_POL, \
451 V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_VSYNC_POS_POL, \
458 V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_VSYNC_POS_POL, \
465 V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_HSYNC_POS_POL, \
473 V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_HSYNC_POS_POL, \
481 V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_VSYNC_POS_POL, \
488 V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_VSYNC_POS_POL, \
495 V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_VSYNC_POS_POL, \
502 V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_HSYNC_POS_POL, \
510 V4L2_INIT_BT_TIMINGS(1280, 960, 0, \
518 V4L2_INIT_BT_TIMINGS(1280, 960, 0, \
526 V4L2_INIT_BT_TIMINGS(1280, 960, 0, V4L2_DV_HSYNC_POS_POL, \
535 V4L2_INIT_BT_TIMINGS(1280, 1024, 0, \
543 V4L2_INIT_BT_TIMINGS(1280, 1024, 0, \
551 V4L2_INIT_BT_TIMINGS(1280, 1024, 0, \
559 V4L2_INIT_BT_TIMINGS(1280, 1024, 0, V4L2_DV_HSYNC_POS_POL, \
567 V4L2_INIT_BT_TIMINGS(1360, 768, 0, \
575 V4L2_INIT_BT_TIMINGS(1360, 768, 0, V4L2_DV_HSYNC_POS_POL, \
583 V4L2_INIT_BT_TIMINGS(1366, 768, 0, \
591 V4L2_INIT_BT_TIMINGS(1366, 768, 0, \
600 V4L2_INIT_BT_TIMINGS(1400, 1050, 0, V4L2_DV_HSYNC_POS_POL, \
608 V4L2_INIT_BT_TIMINGS(1400, 1050, 0, V4L2_DV_VSYNC_POS_POL, \
615 V4L2_INIT_BT_TIMINGS(1400, 1050, 0, V4L2_DV_VSYNC_POS_POL, \
622 V4L2_INIT_BT_TIMINGS(1400, 1050, 0, V4L2_DV_VSYNC_POS_POL, \
629 V4L2_INIT_BT_TIMINGS(1400, 1050, 0, V4L2_DV_HSYNC_POS_POL, \
638 V4L2_INIT_BT_TIMINGS(1440, 900, 0, V4L2_DV_HSYNC_POS_POL, \
646 V4L2_INIT_BT_TIMINGS(1440, 900, 0, V4L2_DV_VSYNC_POS_POL, \
653 V4L2_INIT_BT_TIMINGS(1440, 900, 0, V4L2_DV_VSYNC_POS_POL, \
660 V4L2_INIT_BT_TIMINGS(1440, 900, 0, V4L2_DV_VSYNC_POS_POL, \
667 V4L2_INIT_BT_TIMINGS(1440, 900, 0, V4L2_DV_HSYNC_POS_POL, \
675 V4L2_INIT_BT_TIMINGS(1600, 900, 0, \
684 V4L2_INIT_BT_TIMINGS(1600, 1200, 0, \
692 V4L2_INIT_BT_TIMINGS(1600, 1200, 0, \
700 V4L2_INIT_BT_TIMINGS(1600, 1200, 0, \
708 V4L2_INIT_BT_TIMINGS(1600, 1200, 0, \
716 V4L2_INIT_BT_TIMINGS(1600, 1200, 0, \
724 V4L2_INIT_BT_TIMINGS(1600, 1200, 0, V4L2_DV_HSYNC_POS_POL, \
733 V4L2_INIT_BT_TIMINGS(1680, 1050, 0, V4L2_DV_HSYNC_POS_POL, \
741 V4L2_INIT_BT_TIMINGS(1680, 1050, 0, V4L2_DV_VSYNC_POS_POL, \
748 V4L2_INIT_BT_TIMINGS(1680, 1050, 0, V4L2_DV_VSYNC_POS_POL, \
755 V4L2_INIT_BT_TIMINGS(1680, 1050, 0, V4L2_DV_VSYNC_POS_POL, \
762 V4L2_INIT_BT_TIMINGS(1680, 1050, 0, V4L2_DV_HSYNC_POS_POL, \
770 V4L2_INIT_BT_TIMINGS(1792, 1344, 0, V4L2_DV_VSYNC_POS_POL, \
777 V4L2_INIT_BT_TIMINGS(1792, 1344, 0, V4L2_DV_VSYNC_POS_POL, \
784 V4L2_INIT_BT_TIMINGS(1792, 1344, 0, V4L2_DV_HSYNC_POS_POL, \
792 V4L2_INIT_BT_TIMINGS(1856, 1392, 0, V4L2_DV_VSYNC_POS_POL, \
799 V4L2_INIT_BT_TIMINGS(1856, 1392, 0, V4L2_DV_VSYNC_POS_POL, \
806 V4L2_INIT_BT_TIMINGS(1856, 1392, 0, V4L2_DV_HSYNC_POS_POL, \
817 V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_HSYNC_POS_POL, \
825 V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_VSYNC_POS_POL, \
832 V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_VSYNC_POS_POL, \
839 V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_VSYNC_POS_POL, \
846 V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_HSYNC_POS_POL, \
854 V4L2_INIT_BT_TIMINGS(1920, 1440, 0, V4L2_DV_VSYNC_POS_POL, \
861 V4L2_INIT_BT_TIMINGS(1920, 1440, 0, V4L2_DV_VSYNC_POS_POL, \
868 V4L2_INIT_BT_TIMINGS(1920, 1440, 0, V4L2_DV_HSYNC_POS_POL, \
876 V4L2_INIT_BT_TIMINGS(2048, 1152, 0, \
885 V4L2_INIT_BT_TIMINGS(2560, 1600, 0, V4L2_DV_HSYNC_POS_POL, \
893 V4L2_INIT_BT_TIMINGS(2560, 1600, 0, V4L2_DV_VSYNC_POS_POL, \
900 V4L2_INIT_BT_TIMINGS(2560, 1600, 0, V4L2_DV_VSYNC_POS_POL, \
907 V4L2_INIT_BT_TIMINGS(2560, 1600, 0, V4L2_DV_VSYNC_POS_POL, \
914 V4L2_INIT_BT_TIMINGS(2560, 1600, 0, V4L2_DV_HSYNC_POS_POL, \
923 V4L2_INIT_BT_TIMINGS(4096, 2160, 0, V4L2_DV_HSYNC_POS_POL, \
931 V4L2_INIT_BT_TIMINGS(4096, 2160, 0, V4L2_DV_HSYNC_POS_POL, \