Lines Matching defs:mlx4_caps
487 struct mlx4_caps { struct
488 u64 fw_ver;
489 u32 function;
490 int num_ports;
491 int vl_cap[MLX4_MAX_PORTS + 1];
492 int ib_mtu_cap[MLX4_MAX_PORTS + 1];
493 __be32 ib_port_def_cap[MLX4_MAX_PORTS + 1];
494 u64 def_mac[MLX4_MAX_PORTS + 1];
495 int eth_mtu_cap[MLX4_MAX_PORTS + 1];
496 int gid_table_len[MLX4_MAX_PORTS + 1];
497 int pkey_table_len[MLX4_MAX_PORTS + 1];
498 int trans_type[MLX4_MAX_PORTS + 1];
499 int vendor_oui[MLX4_MAX_PORTS + 1];
500 int wavelength[MLX4_MAX_PORTS + 1];
501 u64 trans_code[MLX4_MAX_PORTS + 1];
502 int local_ca_ack_delay;
503 int num_uars;
504 u32 uar_page_size;
505 int bf_reg_size;
506 int bf_regs_per_page;
507 int max_sq_sg;
508 int max_rq_sg;
509 int num_qps;
510 int max_wqes;
511 int max_sq_desc_sz;
512 int max_rq_desc_sz;
513 int max_qp_init_rdma;
514 int max_qp_dest_rdma;
515 u32 *qp0_qkey;
516 u32 *qp0_proxy;
517 u32 *qp1_proxy;
518 u32 *qp0_tunnel;
519 u32 *qp1_tunnel;
520 int num_srqs;
521 int max_srq_wqes;
522 int max_srq_sge;
523 int reserved_srqs;
524 int num_cqs;
525 int max_cqes;
526 int reserved_cqs;
527 int num_sys_eqs;
528 int num_eqs;
529 int reserved_eqs;
530 int num_comp_vectors;
531 int comp_pool;
532 int num_mpts;
533 int max_fmr_maps;
534 int num_mtts;
535 int fmr_reserved_mtts;
536 int reserved_mtts;
537 int reserved_mrws;
538 int reserved_uars;
539 int num_mgms;
540 int num_amgms;
541 int reserved_mcgs;
542 int num_qp_per_mgm;
543 int steering_mode;
544 int dmfs_high_steer_mode;
545 int fs_log_max_ucast_qp_range_size;
546 int num_pds;
547 int reserved_pds;
548 int max_xrcds;
549 int reserved_xrcds;
550 int mtt_entry_sz;
551 u32 max_msg_sz;
552 u32 page_size_cap;
553 u64 flags;
554 u64 flags2;
555 u32 bmme_flags;
556 u32 reserved_lkey;
557 u16 stat_rate_support;
558 u8 port_width_cap[MLX4_MAX_PORTS + 1];
559 int max_gso_sz;
560 int max_rss_tbl_sz;
561 int reserved_qps_cnt[MLX4_NUM_QP_REGION];
562 int reserved_qps;
563 int reserved_qps_base[MLX4_NUM_QP_REGION];
564 int log_num_macs;
565 int log_num_vlans;
566 enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1];
567 u8 supported_type[MLX4_MAX_PORTS + 1];
568 u8 suggested_type[MLX4_MAX_PORTS + 1];
569 u8 default_sense[MLX4_MAX_PORTS + 1];
570 u32 port_mask[MLX4_MAX_PORTS + 1];
571 enum mlx4_port_type possible_type[MLX4_MAX_PORTS + 1];
572 u32 max_counters;
573 u8 port_ib_mtu[MLX4_MAX_PORTS + 1];
574 u16 sqp_demux;
575 u32 eqe_size;
576 u32 cqe_size;
577 u8 eqe_factor;
578 u32 userspace_caps; /* userspace must be aware of these */
579 u32 function_caps; /* VFs must be aware of these */
580 u16 hca_core_clock;
581 u64 phys_port_id[MLX4_MAX_PORTS + 1];
582 int tunnel_offload_mode;
583 u8 rx_checksum_flags_port[MLX4_MAX_PORTS + 1];
584 u8 alloc_res_qp_mask;
585 u32 dmfs_high_rate_qpn_base;
586 u32 dmfs_high_rate_qpn_range;
587 u32 vf_caps;
588 struct mlx4_rate_limit_caps rl_caps;