Lines Matching refs:clk_hw

138 	struct clk_hw		hw;
228 typedef void (*ti_of_clk_init_cb_t)(struct clk_hw *, struct device_node *);
263 int omap3_noncore_dpll_enable(struct clk_hw *hw);
264 void omap3_noncore_dpll_disable(struct clk_hw *hw);
265 int omap3_noncore_dpll_set_parent(struct clk_hw *hw, u8 index);
266 int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,
268 int omap3_noncore_dpll_set_rate_and_parent(struct clk_hw *hw,
272 long omap3_noncore_dpll_determine_rate(struct clk_hw *hw,
277 				       struct clk_hw **best_parent_clk);
278 unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw,
280 long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw,
283 long omap4_dpll_regm4xen_determine_rate(struct clk_hw *hw,
288 					struct clk_hw **best_parent_clk);
289 u8 omap2_init_dpll_parent(struct clk_hw *hw);
290 unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long parent_rate);
291 long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate,
293 void omap2_init_clk_clkdm(struct clk_hw *clk);
294 unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
296 int omap3_clkoutx2_set_rate(struct clk_hw *hw, unsigned long rate,
298 long omap3_clkoutx2_round_rate(struct clk_hw *hw, unsigned long rate,
300 int omap2_clkops_enable_clkdm(struct clk_hw *hw);
301 void omap2_clkops_disable_clkdm(struct clk_hw *hw);
304 int omap3_dpll4_set_rate(struct clk_hw *clk, unsigned long rate,
306 int omap3_dpll4_set_rate_and_parent(struct clk_hw *hw, unsigned long rate,
308 int omap2_dflt_clk_enable(struct clk_hw *hw);
309 void omap2_dflt_clk_disable(struct clk_hw *hw);
310 int omap2_dflt_clk_is_enabled(struct clk_hw *hw);
312 unsigned long omap2_dpllcore_recalc(struct clk_hw *hw,
314 int omap2_reprogram_dpllcore(struct clk_hw *clk, unsigned long rate,
316 void omap2xxx_clkt_dpllcore_init(struct clk_hw *hw);
324 int ti_clk_retry_init(struct device_node *node, struct clk_hw *hw,
327 int ti_clk_add_component(struct device_node *node, struct clk_hw *hw, int type);