560 	unsigned int temp_ctl = 0;  in tsi148_slave_set()  local
623 	temp_ctl = ioread32be(bridge->base + TSI148_LCSR_IT[i] +  in tsi148_slave_set()
625 	temp_ctl &= ~TSI148_LCSR_ITAT_EN;  in tsi148_slave_set()
626 	iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_IT[i] +  in tsi148_slave_set()
644 	temp_ctl &= ~TSI148_LCSR_ITAT_2eSSTM_M;  in tsi148_slave_set()
647 		temp_ctl |= TSI148_LCSR_ITAT_2eSSTM_160;  in tsi148_slave_set()
650 		temp_ctl |= TSI148_LCSR_ITAT_2eSSTM_267;  in tsi148_slave_set()
653 		temp_ctl |= TSI148_LCSR_ITAT_2eSSTM_320;  in tsi148_slave_set()
658 	temp_ctl &= ~(0x1F << 7);  in tsi148_slave_set()
660 		temp_ctl |= TSI148_LCSR_ITAT_BLT;  in tsi148_slave_set()
662 		temp_ctl |= TSI148_LCSR_ITAT_MBLT;  in tsi148_slave_set()
664 		temp_ctl |= TSI148_LCSR_ITAT_2eVME;  in tsi148_slave_set()
666 		temp_ctl |= TSI148_LCSR_ITAT_2eSST;  in tsi148_slave_set()
668 		temp_ctl |= TSI148_LCSR_ITAT_2eSSTB;  in tsi148_slave_set()
671 	temp_ctl &= ~TSI148_LCSR_ITAT_AS_M;  in tsi148_slave_set()
672 	temp_ctl |= addr;  in tsi148_slave_set()
674 	temp_ctl &= ~0xF;  in tsi148_slave_set()
676 		temp_ctl |= TSI148_LCSR_ITAT_SUPR ;  in tsi148_slave_set()
678 		temp_ctl |= TSI148_LCSR_ITAT_NPRIV;  in tsi148_slave_set()
680 		temp_ctl |= TSI148_LCSR_ITAT_PGM;  in tsi148_slave_set()
682 		temp_ctl |= TSI148_LCSR_ITAT_DATA;  in tsi148_slave_set()
685 	iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_IT[i] +  in tsi148_slave_set()
689 		temp_ctl |= TSI148_LCSR_ITAT_EN;  in tsi148_slave_set()
691 	iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_IT[i] +  in tsi148_slave_set()
899 	unsigned int temp_ctl = 0;  in tsi148_master_set()  local
989 	temp_ctl = ioread32be(bridge->base + TSI148_LCSR_OT[i] +  in tsi148_master_set()
991 	temp_ctl &= ~TSI148_LCSR_OTAT_EN;  in tsi148_master_set()
992 	iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_OT[i] +  in tsi148_master_set()
996 	temp_ctl &= ~TSI148_LCSR_OTAT_2eSSTM_M;  in tsi148_master_set()
999 		temp_ctl |= TSI148_LCSR_OTAT_2eSSTM_160;  in tsi148_master_set()
1002 		temp_ctl |= TSI148_LCSR_OTAT_2eSSTM_267;  in tsi148_master_set()
1005 		temp_ctl |= TSI148_LCSR_OTAT_2eSSTM_320;  in tsi148_master_set()
1011 		temp_ctl &= ~TSI148_LCSR_OTAT_TM_M;  in tsi148_master_set()
1012 		temp_ctl |= TSI148_LCSR_OTAT_TM_BLT;  in tsi148_master_set()
1015 		temp_ctl &= ~TSI148_LCSR_OTAT_TM_M;  in tsi148_master_set()
1016 		temp_ctl |= TSI148_LCSR_OTAT_TM_MBLT;  in tsi148_master_set()
1019 		temp_ctl &= ~TSI148_LCSR_OTAT_TM_M;  in tsi148_master_set()
1020 		temp_ctl |= TSI148_LCSR_OTAT_TM_2eVME;  in tsi148_master_set()
1023 		temp_ctl &= ~TSI148_LCSR_OTAT_TM_M;  in tsi148_master_set()
1024 		temp_ctl |= TSI148_LCSR_OTAT_TM_2eSST;  in tsi148_master_set()
1029 		temp_ctl &= ~TSI148_LCSR_OTAT_TM_M;  in tsi148_master_set()
1030 		temp_ctl |= TSI148_LCSR_OTAT_TM_2eSSTB;  in tsi148_master_set()
1034 	temp_ctl &= ~TSI148_LCSR_OTAT_DBW_M;  in tsi148_master_set()
1037 		temp_ctl |= TSI148_LCSR_OTAT_DBW_16;  in tsi148_master_set()
1040 		temp_ctl |= TSI148_LCSR_OTAT_DBW_32;  in tsi148_master_set()
1050 	temp_ctl &= ~TSI148_LCSR_OTAT_AMODE_M;  in tsi148_master_set()
1053 		temp_ctl |= TSI148_LCSR_OTAT_AMODE_A16;  in tsi148_master_set()
1056 		temp_ctl |= TSI148_LCSR_OTAT_AMODE_A24;  in tsi148_master_set()
1059 		temp_ctl |= TSI148_LCSR_OTAT_AMODE_A32;  in tsi148_master_set()
1062 		temp_ctl |= TSI148_LCSR_OTAT_AMODE_A64;  in tsi148_master_set()
1065 		temp_ctl |= TSI148_LCSR_OTAT_AMODE_CRCSR;  in tsi148_master_set()
1068 		temp_ctl |= TSI148_LCSR_OTAT_AMODE_USER1;  in tsi148_master_set()
1071 		temp_ctl |= TSI148_LCSR_OTAT_AMODE_USER2;  in tsi148_master_set()
1074 		temp_ctl |= TSI148_LCSR_OTAT_AMODE_USER3;  in tsi148_master_set()
1077 		temp_ctl |= TSI148_LCSR_OTAT_AMODE_USER4;  in tsi148_master_set()
1087 	temp_ctl &= ~(3<<4);  in tsi148_master_set()
1089 		temp_ctl |= TSI148_LCSR_OTAT_SUP;  in tsi148_master_set()
1091 		temp_ctl |= TSI148_LCSR_OTAT_PGM;  in tsi148_master_set()
1108 	iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_OT[i] +  in tsi148_master_set()
1112 		temp_ctl |= TSI148_LCSR_OTAT_EN;  in tsi148_master_set()
1114 	iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_OT[i] +  in tsi148_master_set()