Lines Matching refs:dwidth
895 u32 cycle, u32 dwidth) in tsi148_master_set() argument
1035 switch (dwidth) { in tsi148_master_set()
1137 u32 *cycle, u32 *dwidth) in __tsi148_master_get() argument
1178 *dwidth = 0; in __tsi148_master_get()
1237 *dwidth = VME_D16; in __tsi148_master_get()
1239 *dwidth = VME_D32; in __tsi148_master_get()
1247 u32 *cycle, u32 *dwidth) in tsi148_master_get() argument
1254 cycle, dwidth); in tsi148_master_get()
1266 u32 aspace, cycle, dwidth; in tsi148_master_read() local
1324 &dwidth); in tsi148_master_read()
1349 u32 aspace, cycle, dwidth; in tsi148_master_write() local
1421 &dwidth); in tsi148_master_write()
1504 u32 aspace, u32 cycle, u32 dwidth) in tsi148_dma_set_vme_src_attributes() argument
1546 switch (dwidth) { in tsi148_dma_set_vme_src_attributes()
1604 u32 aspace, u32 cycle, u32 dwidth) in tsi148_dma_set_vme_dest_attributes() argument
1646 switch (dwidth) { in tsi148_dma_set_vme_dest_attributes()
1782 vme_attr->aspace, vme_attr->cycle, vme_attr->dwidth); in tsi148_dma_list_add()
1819 vme_attr->aspace, vme_attr->cycle, vme_attr->dwidth); in tsi148_dma_list_add()