77 static u32 tsi148_DMA_irqhandler(struct tsi148_driver *bridge,  in tsi148_DMA_irqhandler()  argument
83 		wake_up(&bridge->dma_queue[0]);  in tsi148_DMA_irqhandler()
87 		wake_up(&bridge->dma_queue[1]);  in tsi148_DMA_irqhandler()
97 static u32 tsi148_LM_irqhandler(struct tsi148_driver *bridge, u32 stat)  in tsi148_LM_irqhandler()  argument
105 			bridge->lm_callback[i](i);  in tsi148_LM_irqhandler()
123 	struct tsi148_driver *bridge;  in tsi148_MB_irqhandler()  local
125 	bridge = tsi148_bridge->driver_priv;  in tsi148_MB_irqhandler()
129 			val = ioread32be(bridge->base +	TSI148_GCSR_MBOX[i]);  in tsi148_MB_irqhandler()
144 	struct tsi148_driver *bridge;  in tsi148_PERR_irqhandler()  local
146 	bridge = tsi148_bridge->driver_priv;  in tsi148_PERR_irqhandler()
150 		ioread32be(bridge->base + TSI148_LCSR_EDPAU),  in tsi148_PERR_irqhandler()
151 		ioread32be(bridge->base + TSI148_LCSR_EDPAL),  in tsi148_PERR_irqhandler()
152 		ioread32be(bridge->base + TSI148_LCSR_EDPAT));  in tsi148_PERR_irqhandler()
156 		ioread32be(bridge->base + TSI148_LCSR_EDPXA),  in tsi148_PERR_irqhandler()
157 		ioread32be(bridge->base + TSI148_LCSR_EDPXS));  in tsi148_PERR_irqhandler()
159 	iowrite32be(TSI148_LCSR_EDPAT_EDPCL, bridge->base + TSI148_LCSR_EDPAT);  in tsi148_PERR_irqhandler()
173 	struct tsi148_driver *bridge;  in tsi148_VERR_irqhandler()  local
175 	bridge = tsi148_bridge->driver_priv;  in tsi148_VERR_irqhandler()
177 	error_addr_high = ioread32be(bridge->base + TSI148_LCSR_VEAU);  in tsi148_VERR_irqhandler()
178 	error_addr_low = ioread32be(bridge->base + TSI148_LCSR_VEAL);  in tsi148_VERR_irqhandler()
179 	error_attrib = ioread32be(bridge->base + TSI148_LCSR_VEAT);  in tsi148_VERR_irqhandler()
208 	iowrite32be(TSI148_LCSR_VEAT_VESCL, bridge->base + TSI148_LCSR_VEAT);  in tsi148_VERR_irqhandler()
216 static u32 tsi148_IACK_irqhandler(struct tsi148_driver *bridge)  in tsi148_IACK_irqhandler()  argument
218 	wake_up(&bridge->iack_queue);  in tsi148_IACK_irqhandler()
230 	struct tsi148_driver *bridge;  in tsi148_VIRQ_irqhandler()  local
232 	bridge = tsi148_bridge->driver_priv;  in tsi148_VIRQ_irqhandler()
241 			vec = ioread8(bridge->base + TSI148_LCSR_VIACK[i] + 3);  in tsi148_VIRQ_irqhandler()
260 	struct tsi148_driver *bridge;  in tsi148_irqhandler()  local
264 	bridge = tsi148_bridge->driver_priv;  in tsi148_irqhandler()
267 	enable = ioread32be(bridge->base + TSI148_LCSR_INTEO);  in tsi148_irqhandler()
268 	stat = ioread32be(bridge->base + TSI148_LCSR_INTS);  in tsi148_irqhandler()
279 		serviced |= tsi148_DMA_irqhandler(bridge, stat);  in tsi148_irqhandler()
284 		serviced |= tsi148_LM_irqhandler(bridge, stat);  in tsi148_irqhandler()
301 		serviced |= tsi148_IACK_irqhandler(bridge);  in tsi148_irqhandler()
311 	iowrite32be(serviced, bridge->base + TSI148_LCSR_INTC);  in tsi148_irqhandler()
321 	struct tsi148_driver *bridge;  in tsi148_irq_init()  local
325 	bridge = tsi148_bridge->driver_priv;  in tsi148_irq_init()
376 	iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO);  in tsi148_irq_init()
377 	iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEN);  in tsi148_irq_init()
385 	struct tsi148_driver *bridge = tsi148_bridge->driver_priv;  in tsi148_irq_exit()  local
388 	iowrite32be(0x0, bridge->base + TSI148_LCSR_INTEO);  in tsi148_irq_exit()
389 	iowrite32be(0x0, bridge->base + TSI148_LCSR_INTEN);  in tsi148_irq_exit()
392 	iowrite32be(0xFFFFFFFF, bridge->base + TSI148_LCSR_INTC);  in tsi148_irq_exit()
401 static int tsi148_iack_received(struct tsi148_driver *bridge)  in tsi148_iack_received()  argument
405 	tmp = ioread32be(bridge->base + TSI148_LCSR_VICR);  in tsi148_iack_received()
421 	struct tsi148_driver *bridge;  in tsi148_irq_set()  local
423 	bridge = tsi148_bridge->driver_priv;  in tsi148_irq_set()
427 		tmp = ioread32be(bridge->base + TSI148_LCSR_INTEN);  in tsi148_irq_set()
429 		iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEN);  in tsi148_irq_set()
431 		tmp = ioread32be(bridge->base + TSI148_LCSR_INTEO);  in tsi148_irq_set()
433 		iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO);  in tsi148_irq_set()
440 		tmp = ioread32be(bridge->base + TSI148_LCSR_INTEO);  in tsi148_irq_set()
442 		iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO);  in tsi148_irq_set()
444 		tmp = ioread32be(bridge->base + TSI148_LCSR_INTEN);  in tsi148_irq_set()
446 		iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEN);  in tsi148_irq_set()
458 	struct tsi148_driver *bridge;  in tsi148_irq_generate()  local
460 	bridge = tsi148_bridge->driver_priv;  in tsi148_irq_generate()
462 	mutex_lock(&bridge->vme_int);  in tsi148_irq_generate()
465 	tmp = ioread32be(bridge->base + TSI148_LCSR_VICR);  in tsi148_irq_generate()
470 	iowrite32be(tmp, bridge->base + TSI148_LCSR_VICR);  in tsi148_irq_generate()
474 	iowrite32be(tmp, bridge->base + TSI148_LCSR_VICR);  in tsi148_irq_generate()
477 	wait_event_interruptible(bridge->iack_queue,  in tsi148_irq_generate()
478 		tsi148_iack_received(bridge));  in tsi148_irq_generate()
480 	mutex_unlock(&bridge->vme_int);  in tsi148_irq_generate()
566 	struct tsi148_driver *bridge;  in tsi148_slave_set()  local
569 	bridge = tsi148_bridge->driver_priv;  in tsi148_slave_set()
623 	temp_ctl = ioread32be(bridge->base + TSI148_LCSR_IT[i] +  in tsi148_slave_set()
626 	iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_IT[i] +  in tsi148_slave_set()
630 	iowrite32be(vme_base_high, bridge->base + TSI148_LCSR_IT[i] +  in tsi148_slave_set()
632 	iowrite32be(vme_base_low, bridge->base + TSI148_LCSR_IT[i] +  in tsi148_slave_set()
634 	iowrite32be(vme_bound_high, bridge->base + TSI148_LCSR_IT[i] +  in tsi148_slave_set()
636 	iowrite32be(vme_bound_low, bridge->base + TSI148_LCSR_IT[i] +  in tsi148_slave_set()
638 	iowrite32be(pci_offset_high, bridge->base + TSI148_LCSR_IT[i] +  in tsi148_slave_set()
640 	iowrite32be(pci_offset_low, bridge->base + TSI148_LCSR_IT[i] +  in tsi148_slave_set()
685 	iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_IT[i] +  in tsi148_slave_set()
691 	iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_IT[i] +  in tsi148_slave_set()
709 	struct tsi148_driver *bridge;  in tsi148_slave_get()  local
711 	bridge = image->parent->driver_priv;  in tsi148_slave_get()
716 	ctl = ioread32be(bridge->base + TSI148_LCSR_IT[i] +  in tsi148_slave_get()
719 	vme_base_high = ioread32be(bridge->base + TSI148_LCSR_IT[i] +  in tsi148_slave_get()
721 	vme_base_low = ioread32be(bridge->base + TSI148_LCSR_IT[i] +  in tsi148_slave_get()
723 	vme_bound_high = ioread32be(bridge->base + TSI148_LCSR_IT[i] +  in tsi148_slave_get()
725 	vme_bound_low = ioread32be(bridge->base + TSI148_LCSR_IT[i] +  in tsi148_slave_get()
727 	pci_offset_high = ioread32be(bridge->base + TSI148_LCSR_IT[i] +  in tsi148_slave_get()
729 	pci_offset_low = ioread32be(bridge->base + TSI148_LCSR_IT[i] +  in tsi148_slave_get()
905 	struct tsi148_driver *bridge;  in tsi148_master_set()  local
911 	bridge = tsi148_bridge->driver_priv;  in tsi148_master_set()
989 	temp_ctl = ioread32be(bridge->base + TSI148_LCSR_OT[i] +  in tsi148_master_set()
992 	iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_OT[i] +  in tsi148_master_set()
1094 	iowrite32be(pci_base_high, bridge->base + TSI148_LCSR_OT[i] +  in tsi148_master_set()
1096 	iowrite32be(pci_base_low, bridge->base + TSI148_LCSR_OT[i] +  in tsi148_master_set()
1098 	iowrite32be(pci_bound_high, bridge->base + TSI148_LCSR_OT[i] +  in tsi148_master_set()
1100 	iowrite32be(pci_bound_low, bridge->base + TSI148_LCSR_OT[i] +  in tsi148_master_set()
1102 	iowrite32be(vme_offset_high, bridge->base + TSI148_LCSR_OT[i] +  in tsi148_master_set()
1104 	iowrite32be(vme_offset_low, bridge->base + TSI148_LCSR_OT[i] +  in tsi148_master_set()
1108 	iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_OT[i] +  in tsi148_master_set()
1114 	iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_OT[i] +  in tsi148_master_set()
1145 	struct tsi148_driver *bridge;  in __tsi148_master_get()  local
1147 	bridge = image->parent->driver_priv;  in __tsi148_master_get()
1151 	ctl = ioread32be(bridge->base + TSI148_LCSR_OT[i] +  in __tsi148_master_get()
1154 	pci_base_high = ioread32be(bridge->base + TSI148_LCSR_OT[i] +  in __tsi148_master_get()
1156 	pci_base_low = ioread32be(bridge->base + TSI148_LCSR_OT[i] +  in __tsi148_master_get()
1158 	pci_bound_high = ioread32be(bridge->base + TSI148_LCSR_OT[i] +  in __tsi148_master_get()
1160 	pci_bound_low = ioread32be(bridge->base + TSI148_LCSR_OT[i] +  in __tsi148_master_get()
1162 	vme_offset_high = ioread32be(bridge->base + TSI148_LCSR_OT[i] +  in __tsi148_master_get()
1164 	vme_offset_low = ioread32be(bridge->base + TSI148_LCSR_OT[i] +  in __tsi148_master_get()
1356 	struct tsi148_driver *bridge;  in tsi148_master_write()  local
1360 	bridge = tsi148_bridge->driver_priv;  in tsi148_master_write()
1423 	ioread16(bridge->flush_image->kern_base + 0x7F000);  in tsi148_master_write()
1455 	struct tsi148_driver *bridge;  in tsi148_master_rmw()  local
1457 	bridge = image->parent->driver_priv;  in tsi148_master_rmw()
1463 	mutex_lock(&bridge->vme_rmw);  in tsi148_master_rmw()
1468 	pci_addr_high = ioread32be(bridge->base + TSI148_LCSR_OT[i] +  in tsi148_master_rmw()
1470 	pci_addr_low = ioread32be(bridge->base + TSI148_LCSR_OT[i] +  in tsi148_master_rmw()
1477 	iowrite32be(mask, bridge->base + TSI148_LCSR_RMWEN);  in tsi148_master_rmw()
1478 	iowrite32be(compare, bridge->base + TSI148_LCSR_RMWC);  in tsi148_master_rmw()
1479 	iowrite32be(swap, bridge->base + TSI148_LCSR_RMWS);  in tsi148_master_rmw()
1480 	iowrite32be(pci_addr_high, bridge->base + TSI148_LCSR_RMWAU);  in tsi148_master_rmw()
1481 	iowrite32be(pci_addr_low, bridge->base + TSI148_LCSR_RMWAL);  in tsi148_master_rmw()
1484 	tmp = ioread32be(bridge->base + TSI148_LCSR_VMCTRL);  in tsi148_master_rmw()
1486 	iowrite32be(tmp, bridge->base + TSI148_LCSR_VMCTRL);  in tsi148_master_rmw()
1492 	tmp = ioread32be(bridge->base + TSI148_LCSR_VMCTRL);  in tsi148_master_rmw()
1494 	iowrite32be(tmp, bridge->base + TSI148_LCSR_VMCTRL);  in tsi148_master_rmw()
1498 	mutex_unlock(&bridge->vme_rmw);  in tsi148_master_rmw()
1868 	struct tsi148_driver *bridge;  in tsi148_dma_busy()  local
1870 	bridge = tsi148_bridge->driver_priv;  in tsi148_dma_busy()
1872 	tmp = ioread32be(bridge->base + TSI148_LCSR_DMA[channel] +  in tsi148_dma_busy()
1895 	struct tsi148_driver *bridge;  in tsi148_dma_list_exec()  local
1901 	bridge = tsi148_bridge->driver_priv;  in tsi148_dma_list_exec()
1932 	iowrite32be(bus_addr_high, bridge->base +  in tsi148_dma_list_exec()
1934 	iowrite32be(bus_addr_low, bridge->base +  in tsi148_dma_list_exec()
1937 	dctlreg = ioread32be(bridge->base + TSI148_LCSR_DMA[channel] +  in tsi148_dma_list_exec()
1941 	iowrite32be(dctlreg | TSI148_LCSR_DCTL_DGO, bridge->base +  in tsi148_dma_list_exec()
1944 	wait_event_interruptible(bridge->dma_queue[channel],  in tsi148_dma_list_exec()
1951 	val = ioread32be(bridge->base + TSI148_LCSR_DMA[channel] +  in tsi148_dma_list_exec()
2005 	struct tsi148_driver *bridge;  in tsi148_lm_set()  local
2009 	bridge = tsi148_bridge->driver_priv;  in tsi148_lm_set()
2015 		if (bridge->lm_callback[i] != NULL) {  in tsi148_lm_set()
2054 	iowrite32be(lm_base_high, bridge->base + TSI148_LCSR_LMBAU);  in tsi148_lm_set()
2055 	iowrite32be(lm_base_low, bridge->base + TSI148_LCSR_LMBAL);  in tsi148_lm_set()
2056 	iowrite32be(lm_ctl, bridge->base + TSI148_LCSR_LMAT);  in tsi148_lm_set()
2070 	struct tsi148_driver *bridge;  in tsi148_lm_get()  local
2072 	bridge = lm->parent->driver_priv;  in tsi148_lm_get()
2076 	lm_base_high = ioread32be(bridge->base + TSI148_LCSR_LMBAU);  in tsi148_lm_get()
2077 	lm_base_low = ioread32be(bridge->base + TSI148_LCSR_LMBAL);  in tsi148_lm_get()
2078 	lm_ctl = ioread32be(bridge->base + TSI148_LCSR_LMAT);  in tsi148_lm_get()
2122 	struct tsi148_driver *bridge;  in tsi148_lm_attach()  local
2126 	bridge = tsi148_bridge->driver_priv;  in tsi148_lm_attach()
2131 	lm_ctl = ioread32be(bridge->base + TSI148_LCSR_LMAT);  in tsi148_lm_attach()
2140 	if (bridge->lm_callback[monitor] != NULL) {  in tsi148_lm_attach()
2147 	bridge->lm_callback[monitor] = callback;  in tsi148_lm_attach()
2150 	tmp = ioread32be(bridge->base + TSI148_LCSR_INTEN);  in tsi148_lm_attach()
2152 	iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEN);  in tsi148_lm_attach()
2154 	tmp = ioread32be(bridge->base + TSI148_LCSR_INTEO);  in tsi148_lm_attach()
2156 	iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO);  in tsi148_lm_attach()
2161 		iowrite32be(lm_ctl, bridge->base + TSI148_LCSR_LMAT);  in tsi148_lm_attach()
2175 	struct tsi148_driver *bridge;  in tsi148_lm_detach()  local
2177 	bridge = lm->parent->driver_priv;  in tsi148_lm_detach()
2182 	lm_en = ioread32be(bridge->base + TSI148_LCSR_INTEN);  in tsi148_lm_detach()
2184 	iowrite32be(lm_en, bridge->base + TSI148_LCSR_INTEN);  in tsi148_lm_detach()
2186 	tmp = ioread32be(bridge->base + TSI148_LCSR_INTEO);  in tsi148_lm_detach()
2188 	iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO);  in tsi148_lm_detach()
2191 		 bridge->base + TSI148_LCSR_INTC);  in tsi148_lm_detach()
2194 	bridge->lm_callback[monitor] = NULL;  in tsi148_lm_detach()
2199 		tmp = ioread32be(bridge->base + TSI148_LCSR_LMAT);  in tsi148_lm_detach()
2201 		iowrite32be(tmp, bridge->base + TSI148_LCSR_LMAT);  in tsi148_lm_detach()
2215 	struct tsi148_driver *bridge;  in tsi148_slot_get()  local
2217 	bridge = tsi148_bridge->driver_priv;  in tsi148_slot_get()
2220 		slot = ioread32be(bridge->base + TSI148_LCSR_VSTAT);  in tsi148_slot_get()
2268 	struct tsi148_driver *bridge;  in tsi148_crcsr_init()  local
2270 	bridge = tsi148_bridge->driver_priv;  in tsi148_crcsr_init()
2273 	bridge->crcsr_kernel = pci_zalloc_consistent(pdev, VME_CRCSR_BUF_SIZE,  in tsi148_crcsr_init()
2274 						     &bridge->crcsr_bus);  in tsi148_crcsr_init()
2275 	if (bridge->crcsr_kernel == NULL) {  in tsi148_crcsr_init()
2281 	reg_split(bridge->crcsr_bus, &crcsr_bus_high, &crcsr_bus_low);  in tsi148_crcsr_init()
2283 	iowrite32be(crcsr_bus_high, bridge->base + TSI148_LCSR_CROU);  in tsi148_crcsr_init()
2284 	iowrite32be(crcsr_bus_low, bridge->base + TSI148_LCSR_CROL);  in tsi148_crcsr_init()
2287 	cbar = ioread32be(bridge->base + TSI148_CBAR);  in tsi148_crcsr_init()
2295 		iowrite32be(cbar<<3, bridge->base + TSI148_CBAR);  in tsi148_crcsr_init()
2299 	crat = ioread32be(bridge->base + TSI148_LCSR_CRAT);  in tsi148_crcsr_init()
2305 			bridge->base + TSI148_LCSR_CRAT);  in tsi148_crcsr_init()
2313 		retval = tsi148_master_set(bridge->flush_image, 1,  in tsi148_crcsr_init()
2329 	struct tsi148_driver *bridge;  in tsi148_crcsr_exit()  local
2331 	bridge = tsi148_bridge->driver_priv;  in tsi148_crcsr_exit()
2334 	crat = ioread32be(bridge->base + TSI148_LCSR_CRAT);  in tsi148_crcsr_exit()
2336 		bridge->base + TSI148_LCSR_CRAT);  in tsi148_crcsr_exit()
2339 	iowrite32be(0, bridge->base + TSI148_LCSR_CROU);  in tsi148_crcsr_exit()
2340 	iowrite32be(0, bridge->base + TSI148_LCSR_CROL);  in tsi148_crcsr_exit()
2342 	pci_free_consistent(pdev, VME_CRCSR_BUF_SIZE, bridge->crcsr_kernel,  in tsi148_crcsr_exit()
2343 		bridge->crcsr_bus);  in tsi148_crcsr_exit()
2662 	struct tsi148_driver *bridge;  in tsi148_remove()  local
2665 	bridge = tsi148_bridge->driver_priv;  in tsi148_remove()
2674 		iowrite32be(0, bridge->base + TSI148_LCSR_IT[i] +  in tsi148_remove()
2676 		iowrite32be(0, bridge->base + TSI148_LCSR_OT[i] +  in tsi148_remove()
2683 	iowrite32be(0, bridge->base + TSI148_LCSR_LMAT);  in tsi148_remove()
2688 	iowrite32be(0, bridge->base + TSI148_LCSR_CSRAT);  in tsi148_remove()
2693 	iowrite32be(0xFFFFFFFF, bridge->base + TSI148_LCSR_EDPAT);  in tsi148_remove()
2694 	iowrite32be(0xFFFFFFFF, bridge->base + TSI148_LCSR_VEAT);  in tsi148_remove()
2695 	iowrite32be(0x07000700, bridge->base + TSI148_LCSR_PSTAT);  in tsi148_remove()
2700 	if (ioread32be(bridge->base + TSI148_LCSR_VICR) & 0x800)  in tsi148_remove()
2701 		iowrite32be(0x8000, bridge->base + TSI148_LCSR_VICR);  in tsi148_remove()
2706 	iowrite32be(0x0, bridge->base + TSI148_LCSR_INTM1);  in tsi148_remove()
2707 	iowrite32be(0x0, bridge->base + TSI148_LCSR_INTM2);  in tsi148_remove()
2737 	iounmap(bridge->base);  in tsi148_remove()