346 	unsigned int temp_ctl = 0;  in ca91cx42_slave_set()  local
412 	temp_ctl = ioread32(bridge->base + CA91CX42_VSI_CTL[i]);  in ca91cx42_slave_set()
413 	temp_ctl &= ~CA91CX42_VSI_CTL_EN;  in ca91cx42_slave_set()
414 	iowrite32(temp_ctl, bridge->base + CA91CX42_VSI_CTL[i]);  in ca91cx42_slave_set()
422 	temp_ctl &= ~CA91CX42_VSI_CTL_VAS_M;  in ca91cx42_slave_set()
423 	temp_ctl |= addr;  in ca91cx42_slave_set()
426 	temp_ctl &= ~(CA91CX42_VSI_CTL_PGM_M | CA91CX42_VSI_CTL_SUPER_M);  in ca91cx42_slave_set()
428 		temp_ctl |= CA91CX42_VSI_CTL_SUPER_SUPR;  in ca91cx42_slave_set()
430 		temp_ctl |= CA91CX42_VSI_CTL_SUPER_NPRIV;  in ca91cx42_slave_set()
432 		temp_ctl |= CA91CX42_VSI_CTL_PGM_PGM;  in ca91cx42_slave_set()
434 		temp_ctl |= CA91CX42_VSI_CTL_PGM_DATA;  in ca91cx42_slave_set()
437 	iowrite32(temp_ctl, bridge->base + CA91CX42_VSI_CTL[i]);  in ca91cx42_slave_set()
440 		temp_ctl |= CA91CX42_VSI_CTL_EN;  in ca91cx42_slave_set()
442 	iowrite32(temp_ctl, bridge->base + CA91CX42_VSI_CTL[i]);  in ca91cx42_slave_set()
605 	unsigned int temp_ctl = 0;  in ca91cx42_master_set()  local
660 	temp_ctl = ioread32(bridge->base + CA91CX42_LSI_CTL[i]);  in ca91cx42_master_set()
661 	temp_ctl &= ~CA91CX42_LSI_CTL_EN;  in ca91cx42_master_set()
662 	iowrite32(temp_ctl, bridge->base + CA91CX42_LSI_CTL[i]);  in ca91cx42_master_set()
665 	temp_ctl &= ~CA91CX42_LSI_CTL_VCT_M;  in ca91cx42_master_set()
667 		temp_ctl |= CA91CX42_LSI_CTL_VCT_BLT;  in ca91cx42_master_set()
669 		temp_ctl |= CA91CX42_LSI_CTL_VCT_MBLT;  in ca91cx42_master_set()
672 	temp_ctl &= ~CA91CX42_LSI_CTL_VDW_M;  in ca91cx42_master_set()
675 		temp_ctl |= CA91CX42_LSI_CTL_VDW_D8;  in ca91cx42_master_set()
678 		temp_ctl |= CA91CX42_LSI_CTL_VDW_D16;  in ca91cx42_master_set()
681 		temp_ctl |= CA91CX42_LSI_CTL_VDW_D32;  in ca91cx42_master_set()
684 		temp_ctl |= CA91CX42_LSI_CTL_VDW_D64;  in ca91cx42_master_set()
695 	temp_ctl &= ~CA91CX42_LSI_CTL_VAS_M;  in ca91cx42_master_set()
698 		temp_ctl |= CA91CX42_LSI_CTL_VAS_A16;  in ca91cx42_master_set()
701 		temp_ctl |= CA91CX42_LSI_CTL_VAS_A24;  in ca91cx42_master_set()
704 		temp_ctl |= CA91CX42_LSI_CTL_VAS_A32;  in ca91cx42_master_set()
707 		temp_ctl |= CA91CX42_LSI_CTL_VAS_CRCSR;  in ca91cx42_master_set()
710 		temp_ctl |= CA91CX42_LSI_CTL_VAS_USER1;  in ca91cx42_master_set()
713 		temp_ctl |= CA91CX42_LSI_CTL_VAS_USER2;  in ca91cx42_master_set()
726 	temp_ctl &= ~(CA91CX42_LSI_CTL_PGM_M | CA91CX42_LSI_CTL_SUPER_M);  in ca91cx42_master_set()
728 		temp_ctl |= CA91CX42_LSI_CTL_SUPER_SUPR;  in ca91cx42_master_set()
730 		temp_ctl |= CA91CX42_LSI_CTL_PGM_PGM;  in ca91cx42_master_set()
738 	iowrite32(temp_ctl, bridge->base + CA91CX42_LSI_CTL[i]);  in ca91cx42_master_set()
741 		temp_ctl |= CA91CX42_LSI_CTL_EN;  in ca91cx42_master_set()
743 	iowrite32(temp_ctl, bridge->base + CA91CX42_LSI_CTL[i]);  in ca91cx42_master_set()