1052 	if ((unsigned long)&entry->descriptor & CA91CX42_DCPP_M) {  in ca91cx42_dma_list_add()
1054 			"required: %p\n", &entry->descriptor);  in ca91cx42_dma_list_add()
1059 	memset(&entry->descriptor, 0, sizeof(struct ca91cx42_dma_descriptor));  in ca91cx42_dma_list_add()
1062 		entry->descriptor.dctl |= CA91CX42_DCTL_L2V;  in ca91cx42_dma_list_add()
1099 		entry->descriptor.dctl |= CA91CX42_DCTL_VCT_BLT;  in ca91cx42_dma_list_add()
1104 		entry->descriptor.dctl |= CA91CX42_DCTL_VDW_D8;  in ca91cx42_dma_list_add()
1107 		entry->descriptor.dctl |= CA91CX42_DCTL_VDW_D16;  in ca91cx42_dma_list_add()
1110 		entry->descriptor.dctl |= CA91CX42_DCTL_VDW_D32;  in ca91cx42_dma_list_add()
1113 		entry->descriptor.dctl |= CA91CX42_DCTL_VDW_D64;  in ca91cx42_dma_list_add()
1123 		entry->descriptor.dctl |= CA91CX42_DCTL_VAS_A16;  in ca91cx42_dma_list_add()
1126 		entry->descriptor.dctl |= CA91CX42_DCTL_VAS_A24;  in ca91cx42_dma_list_add()
1129 		entry->descriptor.dctl |= CA91CX42_DCTL_VAS_A32;  in ca91cx42_dma_list_add()
1132 		entry->descriptor.dctl |= CA91CX42_DCTL_VAS_USER1;  in ca91cx42_dma_list_add()
1135 		entry->descriptor.dctl |= CA91CX42_DCTL_VAS_USER2;  in ca91cx42_dma_list_add()
1144 		entry->descriptor.dctl |= CA91CX42_DCTL_SUPER_SUPR;  in ca91cx42_dma_list_add()
1146 		entry->descriptor.dctl |= CA91CX42_DCTL_PGM_PGM;  in ca91cx42_dma_list_add()
1148 	entry->descriptor.dtbc = count;  in ca91cx42_dma_list_add()
1149 	entry->descriptor.dla = pci_attr->address;  in ca91cx42_dma_list_add()
1150 	entry->descriptor.dva = vme_attr->address;  in ca91cx42_dma_list_add()
1151 	entry->descriptor.dcpp = CA91CX42_DCPP_NULL;  in ca91cx42_dma_list_add()
1161 		desc_ptr = virt_to_bus(&entry->descriptor);  in ca91cx42_dma_list_add()
1162 		prev->descriptor.dcpp = desc_ptr & ~CA91CX42_DCPP_M;  in ca91cx42_dma_list_add()
1225 	bus_addr = virt_to_bus(&entry->descriptor);  in ca91cx42_dma_list_exec()