Lines Matching refs:ctl
451 unsigned int i, granularity = 0, ctl = 0; in ca91cx42_slave_get() local
465 ctl = ioread32(bridge->base + CA91CX42_VSI_CTL[i]); in ca91cx42_slave_get()
478 if (ctl & CA91CX42_VSI_CTL_EN) in ca91cx42_slave_get()
481 if ((ctl & CA91CX42_VSI_CTL_VAS_M) == CA91CX42_VSI_CTL_VAS_A16) in ca91cx42_slave_get()
483 if ((ctl & CA91CX42_VSI_CTL_VAS_M) == CA91CX42_VSI_CTL_VAS_A24) in ca91cx42_slave_get()
485 if ((ctl & CA91CX42_VSI_CTL_VAS_M) == CA91CX42_VSI_CTL_VAS_A32) in ca91cx42_slave_get()
487 if ((ctl & CA91CX42_VSI_CTL_VAS_M) == CA91CX42_VSI_CTL_VAS_USER1) in ca91cx42_slave_get()
489 if ((ctl & CA91CX42_VSI_CTL_VAS_M) == CA91CX42_VSI_CTL_VAS_USER2) in ca91cx42_slave_get()
492 if (ctl & CA91CX42_VSI_CTL_SUPER_SUPR) in ca91cx42_slave_get()
494 if (ctl & CA91CX42_VSI_CTL_SUPER_NPRIV) in ca91cx42_slave_get()
496 if (ctl & CA91CX42_VSI_CTL_PGM_PGM) in ca91cx42_slave_get()
498 if (ctl & CA91CX42_VSI_CTL_PGM_DATA) in ca91cx42_slave_get()
760 unsigned int i, ctl; in __ca91cx42_master_get() local
768 ctl = ioread32(bridge->base + CA91CX42_LSI_CTL[i]); in __ca91cx42_master_get()
782 if (ctl & CA91CX42_LSI_CTL_EN) in __ca91cx42_master_get()
786 switch (ctl & CA91CX42_LSI_CTL_VAS_M) { in __ca91cx42_master_get()
809 if (ctl & CA91CX42_LSI_CTL_VCT_BLT) in __ca91cx42_master_get()
814 if (ctl & CA91CX42_LSI_CTL_SUPER_SUPR) in __ca91cx42_master_get()
819 if (ctl & CA91CX42_LSI_CTL_PGM_PGM) in __ca91cx42_master_get()
825 switch (ctl & CA91CX42_LSI_CTL_VDW_M) { in __ca91cx42_master_get()