Lines Matching refs:bridge
57 static u32 ca91cx42_DMA_irqhandler(struct ca91cx42_driver *bridge) in ca91cx42_DMA_irqhandler() argument
59 wake_up(&bridge->dma_queue); in ca91cx42_DMA_irqhandler()
64 static u32 ca91cx42_LM_irqhandler(struct ca91cx42_driver *bridge, u32 stat) in ca91cx42_LM_irqhandler() argument
72 bridge->lm_callback[i](i); in ca91cx42_LM_irqhandler()
81 static u32 ca91cx42_MB_irqhandler(struct ca91cx42_driver *bridge, int mbox_mask) in ca91cx42_MB_irqhandler() argument
83 wake_up(&bridge->mbox_queue); in ca91cx42_MB_irqhandler()
88 static u32 ca91cx42_IACK_irqhandler(struct ca91cx42_driver *bridge) in ca91cx42_IACK_irqhandler() argument
90 wake_up(&bridge->iack_queue); in ca91cx42_IACK_irqhandler()
98 struct ca91cx42_driver *bridge; in ca91cx42_VERR_irqhandler() local
100 bridge = ca91cx42_bridge->driver_priv; in ca91cx42_VERR_irqhandler()
102 val = ioread32(bridge->base + DGCS); in ca91cx42_VERR_irqhandler()
115 struct ca91cx42_driver *bridge; in ca91cx42_LERR_irqhandler() local
117 bridge = ca91cx42_bridge->driver_priv; in ca91cx42_LERR_irqhandler()
119 val = ioread32(bridge->base + DGCS); in ca91cx42_LERR_irqhandler()
133 struct ca91cx42_driver *bridge; in ca91cx42_VIRQ_irqhandler() local
135 bridge = ca91cx42_bridge->driver_priv; in ca91cx42_VIRQ_irqhandler()
140 vec = ioread32(bridge->base + in ca91cx42_VIRQ_irqhandler()
156 struct ca91cx42_driver *bridge; in ca91cx42_irqhandler() local
160 bridge = ca91cx42_bridge->driver_priv; in ca91cx42_irqhandler()
162 enable = ioread32(bridge->base + LINT_EN); in ca91cx42_irqhandler()
163 stat = ioread32(bridge->base + LINT_STAT); in ca91cx42_irqhandler()
172 serviced |= ca91cx42_DMA_irqhandler(bridge); in ca91cx42_irqhandler()
175 serviced |= ca91cx42_LM_irqhandler(bridge, stat); in ca91cx42_irqhandler()
177 serviced |= ca91cx42_MB_irqhandler(bridge, stat); in ca91cx42_irqhandler()
179 serviced |= ca91cx42_IACK_irqhandler(bridge); in ca91cx42_irqhandler()
191 iowrite32(serviced, bridge->base + LINT_STAT); in ca91cx42_irqhandler()
200 struct ca91cx42_driver *bridge; in ca91cx42_irq_init() local
202 bridge = ca91cx42_bridge->driver_priv; in ca91cx42_irq_init()
213 iowrite32(0, bridge->base + VINT_EN); in ca91cx42_irq_init()
216 iowrite32(0, bridge->base + LINT_EN); in ca91cx42_irq_init()
218 iowrite32(0x00FFFFFF, bridge->base + LINT_STAT); in ca91cx42_irq_init()
229 iowrite32(0, bridge->base + LINT_MAP0); in ca91cx42_irq_init()
230 iowrite32(0, bridge->base + LINT_MAP1); in ca91cx42_irq_init()
231 iowrite32(0, bridge->base + LINT_MAP2); in ca91cx42_irq_init()
238 iowrite32(tmp, bridge->base + LINT_EN); in ca91cx42_irq_init()
243 static void ca91cx42_irq_exit(struct ca91cx42_driver *bridge, in ca91cx42_irq_exit() argument
249 iowrite32(0, bridge->base + VINT_EN); in ca91cx42_irq_exit()
252 iowrite32(0, bridge->base + LINT_EN); in ca91cx42_irq_exit()
254 iowrite32(0x00FFFFFF, bridge->base + LINT_STAT); in ca91cx42_irq_exit()
256 ca91cx42_bridge = container_of((void *)bridge, struct vme_bridge, in ca91cx42_irq_exit()
261 static int ca91cx42_iack_received(struct ca91cx42_driver *bridge, int level) in ca91cx42_iack_received() argument
265 tmp = ioread32(bridge->base + LINT_STAT); in ca91cx42_iack_received()
282 struct ca91cx42_driver *bridge; in ca91cx42_irq_set() local
284 bridge = ca91cx42_bridge->driver_priv; in ca91cx42_irq_set()
287 tmp = ioread32(bridge->base + LINT_EN); in ca91cx42_irq_set()
294 iowrite32(tmp, bridge->base + LINT_EN); in ca91cx42_irq_set()
308 struct ca91cx42_driver *bridge; in ca91cx42_irq_generate() local
310 bridge = ca91cx42_bridge->driver_priv; in ca91cx42_irq_generate()
316 mutex_lock(&bridge->vme_int); in ca91cx42_irq_generate()
318 tmp = ioread32(bridge->base + VINT_EN); in ca91cx42_irq_generate()
321 iowrite32(statid << 24, bridge->base + STATID); in ca91cx42_irq_generate()
325 iowrite32(tmp, bridge->base + VINT_EN); in ca91cx42_irq_generate()
328 wait_event_interruptible(bridge->iack_queue, in ca91cx42_irq_generate()
329 ca91cx42_iack_received(bridge, level)); in ca91cx42_irq_generate()
332 tmp = ioread32(bridge->base + VINT_EN); in ca91cx42_irq_generate()
334 iowrite32(tmp, bridge->base + VINT_EN); in ca91cx42_irq_generate()
336 mutex_unlock(&bridge->vme_int); in ca91cx42_irq_generate()
349 struct ca91cx42_driver *bridge; in ca91cx42_slave_set() local
353 bridge = ca91cx42_bridge->driver_priv; in ca91cx42_slave_set()
412 temp_ctl = ioread32(bridge->base + CA91CX42_VSI_CTL[i]); in ca91cx42_slave_set()
414 iowrite32(temp_ctl, bridge->base + CA91CX42_VSI_CTL[i]); in ca91cx42_slave_set()
417 iowrite32(vme_base, bridge->base + CA91CX42_VSI_BS[i]); in ca91cx42_slave_set()
418 iowrite32(vme_bound, bridge->base + CA91CX42_VSI_BD[i]); in ca91cx42_slave_set()
419 iowrite32(pci_offset, bridge->base + CA91CX42_VSI_TO[i]); in ca91cx42_slave_set()
437 iowrite32(temp_ctl, bridge->base + CA91CX42_VSI_CTL[i]); in ca91cx42_slave_set()
442 iowrite32(temp_ctl, bridge->base + CA91CX42_VSI_CTL[i]); in ca91cx42_slave_set()
453 struct ca91cx42_driver *bridge; in ca91cx42_slave_get() local
455 bridge = image->parent->driver_priv; in ca91cx42_slave_get()
465 ctl = ioread32(bridge->base + CA91CX42_VSI_CTL[i]); in ca91cx42_slave_get()
467 *vme_base = ioread32(bridge->base + CA91CX42_VSI_BS[i]); in ca91cx42_slave_get()
468 vme_bound = ioread32(bridge->base + CA91CX42_VSI_BD[i]); in ca91cx42_slave_get()
469 pci_offset = ioread32(bridge->base + CA91CX42_VSI_TO[i]); in ca91cx42_slave_get()
608 struct ca91cx42_driver *bridge; in ca91cx42_master_set() local
612 bridge = ca91cx42_bridge->driver_priv; in ca91cx42_master_set()
660 temp_ctl = ioread32(bridge->base + CA91CX42_LSI_CTL[i]); in ca91cx42_master_set()
662 iowrite32(temp_ctl, bridge->base + CA91CX42_LSI_CTL[i]); in ca91cx42_master_set()
733 iowrite32(pci_base, bridge->base + CA91CX42_LSI_BS[i]); in ca91cx42_master_set()
734 iowrite32(pci_bound, bridge->base + CA91CX42_LSI_BD[i]); in ca91cx42_master_set()
735 iowrite32(vme_offset, bridge->base + CA91CX42_LSI_TO[i]); in ca91cx42_master_set()
738 iowrite32(temp_ctl, bridge->base + CA91CX42_LSI_CTL[i]); in ca91cx42_master_set()
743 iowrite32(temp_ctl, bridge->base + CA91CX42_LSI_CTL[i]); in ca91cx42_master_set()
762 struct ca91cx42_driver *bridge; in __ca91cx42_master_get() local
764 bridge = image->parent->driver_priv; in __ca91cx42_master_get()
768 ctl = ioread32(bridge->base + CA91CX42_LSI_CTL[i]); in __ca91cx42_master_get()
770 pci_base = ioread32(bridge->base + CA91CX42_LSI_BS[i]); in __ca91cx42_master_get()
771 vme_offset = ioread32(bridge->base + CA91CX42_LSI_TO[i]); in __ca91cx42_master_get()
772 pci_bound = ioread32(bridge->base + CA91CX42_LSI_BD[i]); in __ca91cx42_master_get()
980 struct ca91cx42_driver *bridge; in ca91cx42_master_rmw() local
983 bridge = image->parent->driver_priv; in ca91cx42_master_rmw()
990 mutex_lock(&bridge->vme_rmw); in ca91cx42_master_rmw()
1005 iowrite32(0, bridge->base + SCYC_CTL); in ca91cx42_master_rmw()
1008 iowrite32(mask, bridge->base + SCYC_EN); in ca91cx42_master_rmw()
1009 iowrite32(compare, bridge->base + SCYC_CMP); in ca91cx42_master_rmw()
1010 iowrite32(swap, bridge->base + SCYC_SWP); in ca91cx42_master_rmw()
1011 iowrite32(pci_addr, bridge->base + SCYC_ADDR); in ca91cx42_master_rmw()
1014 iowrite32(CA91CX42_SCYC_CTL_CYC_RMW, bridge->base + SCYC_CTL); in ca91cx42_master_rmw()
1020 iowrite32(0, bridge->base + SCYC_CTL); in ca91cx42_master_rmw()
1025 mutex_unlock(&bridge->vme_rmw); in ca91cx42_master_rmw()
1179 struct ca91cx42_driver *bridge; in ca91cx42_dma_busy() local
1181 bridge = ca91cx42_bridge->driver_priv; in ca91cx42_dma_busy()
1183 tmp = ioread32(bridge->base + DGCS); in ca91cx42_dma_busy()
1199 struct ca91cx42_driver *bridge; in ca91cx42_dma_list_exec() local
1203 bridge = ctrlr->parent->driver_priv; in ca91cx42_dma_list_exec()
1229 iowrite32(0, bridge->base + DTBC); in ca91cx42_dma_list_exec()
1230 iowrite32(bus_addr & ~CA91CX42_DCPP_M, bridge->base + DCPP); in ca91cx42_dma_list_exec()
1233 val = ioread32(bridge->base + DGCS); in ca91cx42_dma_list_exec()
1242 iowrite32(val, bridge->base + DGCS); in ca91cx42_dma_list_exec()
1246 iowrite32(val, bridge->base + DGCS); in ca91cx42_dma_list_exec()
1248 wait_event_interruptible(bridge->dma_queue, in ca91cx42_dma_list_exec()
1255 val = ioread32(bridge->base + DGCS); in ca91cx42_dma_list_exec()
1261 val = ioread32(bridge->base + DCTL); in ca91cx42_dma_list_exec()
1300 struct ca91cx42_driver *bridge; in ca91cx42_lm_set() local
1303 bridge = lm->parent->driver_priv; in ca91cx42_lm_set()
1318 if (bridge->lm_callback[i] != NULL) { in ca91cx42_lm_set()
1352 iowrite32(lm_base, bridge->base + LM_BS); in ca91cx42_lm_set()
1353 iowrite32(lm_ctl, bridge->base + LM_CTL); in ca91cx42_lm_set()
1367 struct ca91cx42_driver *bridge; in ca91cx42_lm_get() local
1369 bridge = lm->parent->driver_priv; in ca91cx42_lm_get()
1373 *lm_base = (unsigned long long)ioread32(bridge->base + LM_BS); in ca91cx42_lm_get()
1374 lm_ctl = ioread32(bridge->base + LM_CTL); in ca91cx42_lm_get()
1410 struct ca91cx42_driver *bridge; in ca91cx42_lm_attach() local
1413 bridge = lm->parent->driver_priv; in ca91cx42_lm_attach()
1419 lm_ctl = ioread32(bridge->base + LM_CTL); in ca91cx42_lm_attach()
1427 if (bridge->lm_callback[monitor] != NULL) { in ca91cx42_lm_attach()
1434 bridge->lm_callback[monitor] = callback; in ca91cx42_lm_attach()
1437 tmp = ioread32(bridge->base + LINT_EN); in ca91cx42_lm_attach()
1439 iowrite32(tmp, bridge->base + LINT_EN); in ca91cx42_lm_attach()
1444 iowrite32(lm_ctl, bridge->base + LM_CTL); in ca91cx42_lm_attach()
1458 struct ca91cx42_driver *bridge; in ca91cx42_lm_detach() local
1460 bridge = lm->parent->driver_priv; in ca91cx42_lm_detach()
1465 tmp = ioread32(bridge->base + LINT_EN); in ca91cx42_lm_detach()
1467 iowrite32(tmp, bridge->base + LINT_EN); in ca91cx42_lm_detach()
1470 bridge->base + LINT_STAT); in ca91cx42_lm_detach()
1473 bridge->lm_callback[monitor] = NULL; in ca91cx42_lm_detach()
1478 tmp = ioread32(bridge->base + LM_CTL); in ca91cx42_lm_detach()
1480 iowrite32(tmp, bridge->base + LM_CTL); in ca91cx42_lm_detach()
1491 struct ca91cx42_driver *bridge; in ca91cx42_slot_get() local
1493 bridge = ca91cx42_bridge->driver_priv; in ca91cx42_slot_get()
1496 slot = ioread32(bridge->base + VCSR_BS); in ca91cx42_slot_get()
1540 struct ca91cx42_driver *bridge; in ca91cx42_crcsr_init() local
1542 bridge = ca91cx42_bridge->driver_priv; in ca91cx42_crcsr_init()
1548 iowrite32(geoid << 27, bridge->base + VCSR_BS); in ca91cx42_crcsr_init()
1558 bridge->crcsr_kernel = pci_zalloc_consistent(pdev, VME_CRCSR_BUF_SIZE, in ca91cx42_crcsr_init()
1559 &bridge->crcsr_bus); in ca91cx42_crcsr_init()
1560 if (bridge->crcsr_kernel == NULL) { in ca91cx42_crcsr_init()
1567 iowrite32(bridge->crcsr_bus - crcsr_addr, bridge->base + VCSR_TO); in ca91cx42_crcsr_init()
1569 tmp = ioread32(bridge->base + VCSR_CTL); in ca91cx42_crcsr_init()
1571 iowrite32(tmp, bridge->base + VCSR_CTL); in ca91cx42_crcsr_init()
1580 struct ca91cx42_driver *bridge; in ca91cx42_crcsr_exit() local
1582 bridge = ca91cx42_bridge->driver_priv; in ca91cx42_crcsr_exit()
1585 tmp = ioread32(bridge->base + VCSR_CTL); in ca91cx42_crcsr_exit()
1587 iowrite32(tmp, bridge->base + VCSR_CTL); in ca91cx42_crcsr_exit()
1590 iowrite32(0, bridge->base + VCSR_TO); in ca91cx42_crcsr_exit()
1592 pci_free_consistent(pdev, VME_CRCSR_BUF_SIZE, bridge->crcsr_kernel, in ca91cx42_crcsr_exit()
1593 bridge->crcsr_bus); in ca91cx42_crcsr_exit()
1870 struct ca91cx42_driver *bridge; in ca91cx42_remove() local
1873 bridge = ca91cx42_bridge->driver_priv; in ca91cx42_remove()
1877 iowrite32(0, bridge->base + LINT_EN); in ca91cx42_remove()
1880 iowrite32(0x00800000, bridge->base + LSI0_CTL); in ca91cx42_remove()
1881 iowrite32(0x00800000, bridge->base + LSI1_CTL); in ca91cx42_remove()
1882 iowrite32(0x00800000, bridge->base + LSI2_CTL); in ca91cx42_remove()
1883 iowrite32(0x00800000, bridge->base + LSI3_CTL); in ca91cx42_remove()
1884 iowrite32(0x00800000, bridge->base + LSI4_CTL); in ca91cx42_remove()
1885 iowrite32(0x00800000, bridge->base + LSI5_CTL); in ca91cx42_remove()
1886 iowrite32(0x00800000, bridge->base + LSI6_CTL); in ca91cx42_remove()
1887 iowrite32(0x00800000, bridge->base + LSI7_CTL); in ca91cx42_remove()
1888 iowrite32(0x00F00000, bridge->base + VSI0_CTL); in ca91cx42_remove()
1889 iowrite32(0x00F00000, bridge->base + VSI1_CTL); in ca91cx42_remove()
1890 iowrite32(0x00F00000, bridge->base + VSI2_CTL); in ca91cx42_remove()
1891 iowrite32(0x00F00000, bridge->base + VSI3_CTL); in ca91cx42_remove()
1892 iowrite32(0x00F00000, bridge->base + VSI4_CTL); in ca91cx42_remove()
1893 iowrite32(0x00F00000, bridge->base + VSI5_CTL); in ca91cx42_remove()
1894 iowrite32(0x00F00000, bridge->base + VSI6_CTL); in ca91cx42_remove()
1895 iowrite32(0x00F00000, bridge->base + VSI7_CTL); in ca91cx42_remove()
1930 ca91cx42_irq_exit(bridge, pdev); in ca91cx42_remove()
1932 iounmap(bridge->base); in ca91cx42_remove()