Lines Matching refs:vgabase
128 svga_tilecursor(par->state.vgabase, info, cursor); in vt8623fb_tilecursor()
274 regval = vga_r(par->state.vgabase, VGA_MIS_R); in vt8623_set_pixclock()
275 vga_w(par->state.vgabase, VGA_MIS_W, regval | VGA_MIS_ENB_PLL_LOAD); in vt8623_set_pixclock()
278 vga_wseq(par->state.vgabase, 0x46, (n | (r << 6))); in vt8623_set_pixclock()
279 vga_wseq(par->state.vgabase, 0x47, m); in vt8623_set_pixclock()
284 svga_wseq_mask(par->state.vgabase, 0x40, 0x02, 0x02); in vt8623_set_pixclock()
285 svga_wseq_mask(par->state.vgabase, 0x40, 0x00, 0x02); in vt8623_set_pixclock()
295 void __iomem *vgabase = par->state.vgabase; in vt8623fb_open() local
298 par->state.vgabase = vgabase; in vt8623fb_open()
430 svga_wseq_mask(par->state.vgabase, 0x10, 0x01, 0x01); in vt8623fb_set_par()
431 svga_wcrt_mask(par->state.vgabase, 0x11, 0x00, 0x80); in vt8623fb_set_par()
432 svga_wcrt_mask(par->state.vgabase, 0x47, 0x00, 0x01); in vt8623fb_set_par()
435 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20); in vt8623fb_set_par()
436 svga_wcrt_mask(par->state.vgabase, 0x36, 0x30, 0x30); in vt8623fb_set_par()
437 svga_wcrt_mask(par->state.vgabase, 0x17, 0x00, 0x80); in vt8623fb_set_par()
440 svga_set_default_gfx_regs(par->state.vgabase); in vt8623fb_set_par()
441 svga_set_default_atc_regs(par->state.vgabase); in vt8623fb_set_par()
442 svga_set_default_seq_regs(par->state.vgabase); in vt8623fb_set_par()
443 svga_set_default_crt_regs(par->state.vgabase); in vt8623fb_set_par()
444 svga_wcrt_multi(par->state.vgabase, vt8623_line_compare_regs, 0xFFFFFFFF); in vt8623fb_set_par()
445 svga_wcrt_multi(par->state.vgabase, vt8623_start_address_regs, 0); in vt8623fb_set_par()
447 svga_wcrt_multi(par->state.vgabase, vt8623_offset_regs, offset_value); in vt8623fb_set_par()
448 svga_wseq_multi(par->state.vgabase, vt8623_fetch_count_regs, fetch_value); in vt8623fb_set_par()
451 svga_wcrt_mask(par->state.vgabase, 0x03, 0x00, 0x60); in vt8623fb_set_par()
452 svga_wcrt_mask(par->state.vgabase, 0x05, 0x00, 0x60); in vt8623fb_set_par()
455 svga_wcrt_mask(par->state.vgabase, 0x09, 0x80, 0x80); in vt8623fb_set_par()
457 svga_wcrt_mask(par->state.vgabase, 0x09, 0x00, 0x80); in vt8623fb_set_par()
459 svga_wseq_mask(par->state.vgabase, 0x1E, 0xF0, 0xF0); // DI/DVP bus in vt8623fb_set_par()
460 svga_wseq_mask(par->state.vgabase, 0x2A, 0x0F, 0x0F); // DI/DVP bus in vt8623fb_set_par()
461 svga_wseq_mask(par->state.vgabase, 0x16, 0x08, 0xBF); // FIFO read threshold in vt8623fb_set_par()
462 vga_wseq(par->state.vgabase, 0x17, 0x1F); // FIFO depth in vt8623fb_set_par()
463 vga_wseq(par->state.vgabase, 0x18, 0x4E); in vt8623fb_set_par()
464 svga_wseq_mask(par->state.vgabase, 0x1A, 0x08, 0x08); // enable MMIO ? in vt8623fb_set_par()
466 vga_wcrt(par->state.vgabase, 0x32, 0x00); in vt8623fb_set_par()
467 vga_wcrt(par->state.vgabase, 0x34, 0x00); in vt8623fb_set_par()
468 vga_wcrt(par->state.vgabase, 0x6A, 0x80); in vt8623fb_set_par()
469 vga_wcrt(par->state.vgabase, 0x6A, 0xC0); in vt8623fb_set_par()
471 vga_wgfx(par->state.vgabase, 0x20, 0x00); in vt8623fb_set_par()
472 vga_wgfx(par->state.vgabase, 0x21, 0x00); in vt8623fb_set_par()
473 vga_wgfx(par->state.vgabase, 0x22, 0x00); in vt8623fb_set_par()
480 svga_set_textmode_vga_regs(par->state.vgabase); in vt8623fb_set_par()
481 svga_wseq_mask(par->state.vgabase, 0x15, 0x00, 0xFE); in vt8623fb_set_par()
482 svga_wcrt_mask(par->state.vgabase, 0x11, 0x60, 0x70); in vt8623fb_set_par()
486 vga_wgfx(par->state.vgabase, VGA_GFX_MODE, 0x40); in vt8623fb_set_par()
487 svga_wseq_mask(par->state.vgabase, 0x15, 0x20, 0xFE); in vt8623fb_set_par()
488 svga_wcrt_mask(par->state.vgabase, 0x11, 0x00, 0x70); in vt8623fb_set_par()
492 svga_wseq_mask(par->state.vgabase, 0x15, 0x00, 0xFE); in vt8623fb_set_par()
493 svga_wcrt_mask(par->state.vgabase, 0x11, 0x00, 0x70); in vt8623fb_set_par()
497 svga_wseq_mask(par->state.vgabase, 0x15, 0x22, 0xFE); in vt8623fb_set_par()
501 svga_wseq_mask(par->state.vgabase, 0x15, 0xB6, 0xFE); in vt8623fb_set_par()
505 svga_wseq_mask(par->state.vgabase, 0x15, 0xAE, 0xFE); in vt8623fb_set_par()
513 svga_set_timings(par->state.vgabase, &vt8623_timing_regs, &(info->var), 1, 1, in vt8623fb_set_par()
520 svga_wcrt_mask(par->state.vgabase, 0x17, 0x80, 0x80); in vt8623fb_set_par()
521 svga_wcrt_mask(par->state.vgabase, 0x36, 0x00, 0x30); in vt8623fb_set_par()
522 svga_wseq_mask(par->state.vgabase, 0x01, 0x00, 0x20); in vt8623fb_set_par()
590 svga_wcrt_mask(par->state.vgabase, 0x36, 0x00, 0x30); in vt8623fb_blank()
591 svga_wseq_mask(par->state.vgabase, 0x01, 0x00, 0x20); in vt8623fb_blank()
595 svga_wcrt_mask(par->state.vgabase, 0x36, 0x00, 0x30); in vt8623fb_blank()
596 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20); in vt8623fb_blank()
600 svga_wcrt_mask(par->state.vgabase, 0x36, 0x10, 0x30); in vt8623fb_blank()
601 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20); in vt8623fb_blank()
605 svga_wcrt_mask(par->state.vgabase, 0x36, 0x20, 0x30); in vt8623fb_blank()
606 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20); in vt8623fb_blank()
610 svga_wcrt_mask(par->state.vgabase, 0x36, 0x30, 0x30); in vt8623fb_blank()
611 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20); in vt8623fb_blank()
636 svga_wcrt_multi(par->state.vgabase, vt8623_start_address_regs, offset); in vt8623fb_pan_display()
734 par->state.vgabase = (void __iomem *) (unsigned long) vga_res.start; in vt8623_pci_probe()
737 memsize1 = (vga_rseq(par->state.vgabase, 0x34) + 1) >> 1; in vt8623_pci_probe()
738 memsize2 = vga_rseq(par->state.vgabase, 0x39) << 2; in vt8623_pci_probe()