207 		RegCR6B = viafb_read_reg(VIACR, CR6B);  in viafb_dvi_sense()
208 		viafb_write_reg(CR6B, VIACR, RegCR6B | 0x08);  in viafb_dvi_sense()
212 		RegCR91 = viafb_read_reg(VIACR, CR91);  in viafb_dvi_sense()
213 		viafb_write_reg(CR91, VIACR, 0x1D);  in viafb_dvi_sense()
219 		RegCR93 = viafb_read_reg(VIACR, CR93);  in viafb_dvi_sense()
220 		viafb_write_reg(CR93, VIACR, 0x01);  in viafb_dvi_sense()
233 		RegCR91 = viafb_read_reg(VIACR, CR91);  in viafb_dvi_sense()
234 		viafb_write_reg(CR91, VIACR, 0x1D);  in viafb_dvi_sense()
238 		RegCR9B = viafb_read_reg(VIACR, CR9B);  in viafb_dvi_sense()
239 		viafb_write_reg(CR9B, VIACR, 0x01);  in viafb_dvi_sense()
253 	viafb_write_reg(CR91, VIACR, RegCR91);  in viafb_dvi_sense()
255 		viafb_write_reg(CR6B, VIACR, RegCR6B);  in viafb_dvi_sense()
256 		viafb_write_reg(CR93, VIACR, RegCR93);  in viafb_dvi_sense()
259 		viafb_write_reg(CR9B, VIACR, RegCR9B);  in viafb_dvi_sense()
332 		viafb_write_reg(CRD2, VIACR,  in viafb_dvi_disable()
333 		viafb_read_reg(VIACR, CRD2) | 0x08);  in viafb_dvi_disable()
348 				viafb_write_reg_mask(CR96, VIACR, 0x03,  in dvi_patch_skew_dvp0()
351 				viafb_write_reg_mask(CR96, VIACR, 0x07,  in dvi_patch_skew_dvp0()
358 			viafb_write_reg_mask(CR96, VIACR, 0x07,  in dvi_patch_skew_dvp0()
377 			viafb_write_reg_mask(CR99, VIACR, 0x03, BIT0 + BIT1);  in dvi_patch_skew_dvp_low()
383 			viafb_write_reg_mask(CR99, VIACR, 0x08,  in dvi_patch_skew_dvp_low()
390 			viafb_write_reg_mask(CR99, VIACR, 0x0F,  in dvi_patch_skew_dvp_low()
409 		viafb_write_reg_mask(CR6B, VIACR, 0x01, BIT0);  in viafb_dvi_enable()
410 		viafb_write_reg_mask(CR6C, VIACR, 0x21, BIT0 + BIT5);  in viafb_dvi_enable()
417 			via_write_reg_mask(VIACR, 0x91, 0x00, 0x20);  in viafb_dvi_enable()
422 			viafb_write_reg_mask(CR93, VIACR, 0x21, BIT0 + BIT5);  in viafb_dvi_enable()
430 			via_write_reg_mask(VIACR, 0x91, 0x00, 0x20);  in viafb_dvi_enable()
434 			viafb_write_reg_mask(CR91, VIACR, 0x1f, 0x1f);  in viafb_dvi_enable()
435 			viafb_write_reg_mask(CR88, VIACR, 0x00, BIT6 + BIT0);  in viafb_dvi_enable()
452 			via_write_reg_mask(VIACR, CR97, 0x03, 0x03);  in viafb_dvi_enable()
454 		via_write_reg_mask(VIACR, 0x91, 0x00, 0x20);  in viafb_dvi_enable()
462 		via_write_reg_mask(VIACR, 0x91, 0x00, 0x20);  in viafb_dvi_enable()
467 		viafb_write_reg_mask(CR91, VIACR, 0, BIT7);  in viafb_dvi_enable()
470 		viafb_write_reg_mask(CRD2, VIACR, 0, BIT3);  in viafb_dvi_enable()
476 		viafb_write_reg_mask(CR79, VIACR, 0x00, BIT0);  in viafb_dvi_enable()