157 static inline void t_outb(struct tridentfb_par *p, u8 val, u16 reg)  in t_outb()  function
278 	t_outb(par, x, 0x2125);  in xp_init_accel()
284 	t_outb(par, 3, 0x2126);  in xp_init_accel()
300 				t_outb(par, 0x00, STATUS);  in xp_wait_engine()
316 	t_outb(par, 0x01, OLDCMD);  in xp_fill_rect()
317 	t_outb(par, par->eng_oper, 0x2125);  in xp_fill_rect()
345 	t_outb(par, ROP_S, 0x2127);  in xp_copy_rect()
349 	t_outb(par, 0x01, OLDCMD);  in xp_copy_rect()
451 	t_outb(par, ROP_P, 0x2127);  in tgui_fill_rect()
456 	t_outb(par, 1, OLDCMD);  in tgui_fill_rect()
484 	t_outb(par, ROP_S, 0x2127);  in tgui_copy_rect()
488 	t_outb(par, 1, OLDCMD);  in tgui_copy_rect()
629 	t_outb(par, PCIReg, 0x3D4);  in disable_mmio()
630 	t_outb(par, t_inb(par, 0x3D5) & ~0x01, 0x3D5);  in disable_mmio()
749 		t_outb(par, lo, 0x43C8);  in set_vclk()
750 		t_outb(par, hi, 0x43C9);  in set_vclk()
1058 		t_outb(par, tmp | 0xC0, VGA_MIS_W);  in tridentfb_set_par()
1068 		t_outb(par, tmp, VGA_MIS_W);  in tridentfb_set_par()
1199 	t_outb(par, 0x20, VGA_ATT_W);		/* enable attr */  in tridentfb_set_par()
1219 	t_outb(par, tmp, VGA_PEL_MSK);  in tridentfb_set_par()
1248 		t_outb(par, 0xFF, VGA_PEL_MSK);  in tridentfb_setcolreg()
1249 		t_outb(par, regno, VGA_PEL_IW);  in tridentfb_setcolreg()
1251 		t_outb(par, red >> 10, VGA_PEL_D);  in tridentfb_setcolreg()
1252 		t_outb(par, green >> 10, VGA_PEL_D);  in tridentfb_setcolreg()
1253 		t_outb(par, blue >> 10, VGA_PEL_D);  in tridentfb_setcolreg()
1283 	t_outb(par, 0x04, 0x83C8); /* Read DPMS Control */  in tridentfb_blank()
1312 	t_outb(par, 4, 0x83C8);  in tridentfb_blank()
1313 	t_outb(par, PMCont, 0x83C6);  in tridentfb_blank()