Lines Matching refs:par
167 struct tga_par *par = (struct tga_par *)info->par; in tgafb_check_var() local
169 if (par->tga_type == TGA_TYPE_8PLANE) { in tgafb_check_var()
196 if (var->xres * (par->tga_type == TGA_TYPE_8PLANE ? 1 : 4) % 8) in tgafb_check_var()
234 struct tga_par *par = (struct tga_par *) info->par; local
235 int tga_bus_pci = dev_is_pci(par->dev);
236 int tga_bus_tc = TGA_BUS_TC(par->dev);
257 par->htimings = htimings;
258 par->vtimings = vtimings;
260 par->sync_on_green = !!(info->var.sync & FB_SYNC_ON_GREEN);
263 par->xres = info->var.xres;
264 par->yres = info->var.yres;
265 par->pll_freq = pll_freq = 1000000000 / info->var.pixclock;
266 par->bits_per_pixel = info->var.bits_per_pixel;
267 info->fix.line_length = par->xres * (par->bits_per_pixel >> 3);
269 tga_type = par->tga_type;
272 TGA_WRITE_REG(par, TGA_VALID_VIDEO | TGA_VALID_BLANK, TGA_VALID_REG);
275 while (TGA_READ_REG(par, TGA_CMD_STAT_REG) & 1) /* wait for not busy */
278 TGA_WRITE_REG(par, deep_presets[tga_type] |
279 (par->sync_on_green ? 0x0 : 0x00010000),
281 while (TGA_READ_REG(par, TGA_CMD_STAT_REG) & 1) /* wait for not busy */
286 TGA_WRITE_REG(par, rasterop_presets[tga_type], TGA_RASTEROP_REG);
287 TGA_WRITE_REG(par, mode_presets[tga_type], TGA_MODE_REG);
288 TGA_WRITE_REG(par, base_addr_presets[tga_type], TGA_BASE_ADDR_REG);
291 tgafb_set_pll(par, pll_freq);
294 TGA_WRITE_REG(par, 0xffffffff, TGA_PLANEMASK_REG);
295 TGA_WRITE_REG(par, 0xffffffff, TGA_PIXELMASK_REG);
298 TGA_WRITE_REG(par, htimings, TGA_HORIZ_REG);
299 TGA_WRITE_REG(par, vtimings, TGA_VERT_REG);
305 BT485_WRITE(par, 0xa2 | (par->sync_on_green ? 0x8 : 0x0),
307 BT485_WRITE(par, 0x01, BT485_ADDR_PAL_WRITE);
308 BT485_WRITE(par, 0x14, BT485_CMD_3); /* cursor 64x64 */
309 BT485_WRITE(par, 0x40, BT485_CMD_1);
310 BT485_WRITE(par, 0x20, BT485_CMD_2); /* cursor off, for now */
311 BT485_WRITE(par, 0xff, BT485_PIXEL_MASK);
314 BT485_WRITE(par, 0x00, BT485_ADDR_PAL_WRITE);
315 TGA_WRITE_REG(par, BT485_DATA_PAL, TGA_RAMDAC_SETUP_REG);
318 TGA_WRITE_REG(par, 0x55 | (BT485_DATA_PAL << 8),
320 TGA_WRITE_REG(par, 0x00 | (BT485_DATA_PAL << 8),
322 TGA_WRITE_REG(par, 0x00 | (BT485_DATA_PAL << 8),
324 TGA_WRITE_REG(par, 0x00 | (BT485_DATA_PAL << 8),
331 BT459_WRITE(par, BT459_REG_ACC, BT459_CMD_REG_0, 0x40);
332 BT459_WRITE(par, BT459_REG_ACC, BT459_CMD_REG_1, 0x00);
333 BT459_WRITE(par, BT459_REG_ACC, BT459_CMD_REG_2,
334 (par->sync_on_green ? 0xc0 : 0x40));
336 BT459_WRITE(par, BT459_REG_ACC, BT459_CUR_CMD_REG, 0x00);
339 BT459_LOAD_ADDR(par, 0x0000);
340 TGA_WRITE_REG(par, BT459_PALETTE << 2, TGA_RAMDAC_SETUP_REG);
343 TGA_WRITE_REG(par, 0x55, TGA_RAMDAC_REG);
344 TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG);
345 TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG);
346 TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG);
352 BT463_WRITE(par, BT463_REG_ACC, BT463_CMD_REG_0, 0x40);
353 BT463_WRITE(par, BT463_REG_ACC, BT463_CMD_REG_1, 0x08);
354 BT463_WRITE(par, BT463_REG_ACC, BT463_CMD_REG_2,
355 (par->sync_on_green ? 0xc0 : 0x40));
357 BT463_WRITE(par, BT463_REG_ACC, BT463_READ_MASK_0, 0xff);
358 BT463_WRITE(par, BT463_REG_ACC, BT463_READ_MASK_1, 0xff);
359 BT463_WRITE(par, BT463_REG_ACC, BT463_READ_MASK_2, 0xff);
360 BT463_WRITE(par, BT463_REG_ACC, BT463_READ_MASK_3, 0x0f);
362 BT463_WRITE(par, BT463_REG_ACC, BT463_BLINK_MASK_0, 0x00);
363 BT463_WRITE(par, BT463_REG_ACC, BT463_BLINK_MASK_1, 0x00);
364 BT463_WRITE(par, BT463_REG_ACC, BT463_BLINK_MASK_2, 0x00);
365 BT463_WRITE(par, BT463_REG_ACC, BT463_BLINK_MASK_3, 0x00);
368 BT463_LOAD_ADDR(par, 0x0000);
369 TGA_WRITE_REG(par, BT463_PALETTE << 2, TGA_RAMDAC_SETUP_REG);
375 TGA_WRITE_REG(par, default_red[j], TGA_RAMDAC_REG);
376 TGA_WRITE_REG(par, default_grn[j], TGA_RAMDAC_REG);
377 TGA_WRITE_REG(par, default_blu[j], TGA_RAMDAC_REG);
383 TGA_WRITE_REG(par, 0x55, TGA_RAMDAC_REG);
384 TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG);
385 TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG);
386 TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG);
390 while (!(TGA_READ_REG(par, TGA_INTR_STAT_REG) & 0x01))
392 TGA_WRITE_REG(par, 0x01, TGA_INTR_STAT_REG);
394 while (!(TGA_READ_REG(par, TGA_INTR_STAT_REG) & 0x01))
396 TGA_WRITE_REG(par, 0x01, TGA_INTR_STAT_REG);
398 BT463_LOAD_ADDR(par, BT463_WINDOW_TYPE_BASE);
399 TGA_WRITE_REG(par, BT463_REG_ACC << 2, TGA_RAMDAC_SETUP_REG);
402 TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG);
403 TGA_WRITE_REG(par, 0x01, TGA_RAMDAC_REG);
404 TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG);
410 TGA_WRITE_REG(par, TGA_VALID_VIDEO, TGA_VALID_REG);
427 tgafb_set_pll(struct tga_par *par, int f) argument
433 TGA_WRITE_REG(par, !r, TGA_CLOCK_REG);
445 TGA_WRITE_REG(par, shift & 1, TGA_CLOCK_REG);
446 TGA_WRITE_REG(par, shift >> 1, TGA_CLOCK_REG);
449 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
452 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
453 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
456 TGA_WRITE_REG(par, 1, TGA_CLOCK_REG);
457 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
460 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
461 TGA_WRITE_REG(par, 1, TGA_CLOCK_REG);
464 TGA_WRITE_REG(par, 1, TGA_CLOCK_REG);
465 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
466 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
467 TGA_WRITE_REG(par, 1, TGA_CLOCK_REG);
468 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
469 TGA_WRITE_REG(par, 1, TGA_CLOCK_REG);
496 TGA_WRITE_REG(par, (vm >> r) & 1, TGA_CLOCK_REG);
498 TGA_WRITE_REG(par, (va >> r) & 1, TGA_CLOCK_REG);
500 TGA_WRITE_REG(par, (vr >> r) & 1, TGA_CLOCK_REG);
501 TGA_WRITE_REG(par, ((vr >> 7) & 1)|2, TGA_CLOCK_REG);
518 struct tga_par *par = (struct tga_par *) info->par; local
519 int tga_bus_pci = dev_is_pci(par->dev);
520 int tga_bus_tc = TGA_BUS_TC(par->dev);
528 if (par->tga_type == TGA_TYPE_8PLANE && tga_bus_pci) {
529 BT485_WRITE(par, regno, BT485_ADDR_PAL_WRITE);
530 TGA_WRITE_REG(par, BT485_DATA_PAL, TGA_RAMDAC_SETUP_REG);
531 TGA_WRITE_REG(par, red|(BT485_DATA_PAL<<8),TGA_RAMDAC_REG);
532 TGA_WRITE_REG(par, green|(BT485_DATA_PAL<<8),TGA_RAMDAC_REG);
533 TGA_WRITE_REG(par, blue|(BT485_DATA_PAL<<8),TGA_RAMDAC_REG);
534 } else if (par->tga_type == TGA_TYPE_8PLANE && tga_bus_tc) {
535 BT459_LOAD_ADDR(par, regno);
536 TGA_WRITE_REG(par, BT459_PALETTE << 2, TGA_RAMDAC_SETUP_REG);
537 TGA_WRITE_REG(par, red, TGA_RAMDAC_REG);
538 TGA_WRITE_REG(par, green, TGA_RAMDAC_REG);
539 TGA_WRITE_REG(par, blue, TGA_RAMDAC_REG);
545 BT463_LOAD_ADDR(par, regno);
546 TGA_WRITE_REG(par, BT463_PALETTE << 2, TGA_RAMDAC_SETUP_REG);
547 TGA_WRITE_REG(par, red, TGA_RAMDAC_REG);
548 TGA_WRITE_REG(par, green, TGA_RAMDAC_REG);
549 TGA_WRITE_REG(par, blue, TGA_RAMDAC_REG);
564 struct tga_par *par = (struct tga_par *) info->par; local
570 vhcr = TGA_READ_REG(par, TGA_HORIZ_REG);
571 vvcr = TGA_READ_REG(par, TGA_VERT_REG);
572 vvvr = TGA_READ_REG(par, TGA_VALID_REG);
577 if (par->vesa_blanked) {
578 TGA_WRITE_REG(par, vhcr & 0xbfffffff, TGA_HORIZ_REG);
579 TGA_WRITE_REG(par, vvcr & 0xbfffffff, TGA_VERT_REG);
580 par->vesa_blanked = 0;
582 TGA_WRITE_REG(par, vvvr | TGA_VALID_VIDEO, TGA_VALID_REG);
586 TGA_WRITE_REG(par, vvvr | TGA_VALID_VIDEO | TGA_VALID_BLANK,
591 TGA_WRITE_REG(par, vvcr | 0x40000000, TGA_VERT_REG);
592 TGA_WRITE_REG(par, vvvr | TGA_VALID_BLANK, TGA_VALID_REG);
593 par->vesa_blanked = 1;
597 TGA_WRITE_REG(par, vhcr | 0x40000000, TGA_HORIZ_REG);
598 TGA_WRITE_REG(par, vvvr | TGA_VALID_BLANK, TGA_VALID_REG);
599 par->vesa_blanked = 1;
603 TGA_WRITE_REG(par, vhcr | 0x40000000, TGA_HORIZ_REG);
604 TGA_WRITE_REG(par, vvcr | 0x40000000, TGA_VERT_REG);
605 TGA_WRITE_REG(par, vvvr | TGA_VALID_BLANK, TGA_VALID_REG);
606 par->vesa_blanked = 1;
622 struct tga_par *par = (struct tga_par *) info->par; local
652 regs_base = par->tga_regs_base;
653 fb_base = par->tga_fb_base;
835 struct tga_par *par = (struct tga_par *) info->par; local
858 regs_base = par->tga_regs_base;
859 fb_base = par->tga_fb_base;
922 struct tga_par *par = (struct tga_par *) info->par; local
936 regs_base = par->tga_regs_base;
937 fb_base = par->tga_fb_base;
1053 struct tga_par *par = (struct tga_par *) info->par; local
1054 void __iomem *tga_regs = par->tga_regs_base;
1098 struct tga_par *par = (struct tga_par *) info->par; local
1099 void __iomem *tga_regs = par->tga_regs_base;
1100 void __iomem *tga_fb = par->tga_fb_base;
1148 struct tga_par *par = (struct tga_par *) info->par; local
1194 tga_regs = par->tga_regs_base;
1195 tga_fb = par->tga_fb_base;
1309 struct tga_par *par = (struct tga_par *)info->par; local
1310 int tga_bus_pci = dev_is_pci(par->dev);
1311 int tga_bus_tc = TGA_BUS_TC(par->dev);
1312 u8 tga_type = par->tga_type;
1352 info->fix.smem_start = (size_t) par->tga_fb_base;
1354 info->fix.mmio_start = (size_t) par->tga_regs_base;
1407 struct tga_par *par; local
1424 par = info->par;
1451 par->dev = dev;
1452 par->tga_mem_base = mem_base;
1453 par->tga_fb_base = mem_base + fb_offset_presets[tga_type];
1454 par->tga_regs_base = mem_base + TGA_REGS_OFFSET;
1455 par->tga_type = tga_type;
1457 par->tga_chip_rev = (to_pci_dev(dev))->revision;
1459 par->tga_chip_rev = TGA_READ_REG(par, TGA_START_REG) & 0xff;
1465 info->screen_base = par->tga_fb_base;
1466 info->pseudo_palette = par->palette;
1506 par->tga_chip_rev);
1514 par->tga_chip_rev);
1537 struct tga_par *par; local
1543 par = info->par;
1546 iounmap(par->tga_mem_base);