318 		savage_out32(0x48C18, savage_in32(0x48C18, par) & 0x3FF0, par);  in SavageSetup2DEngine()
320 		savage_out32(0x48C14,  in SavageSetup2DEngine()
324 		savage_out32(0x48C10, 0x78207220, par);  in SavageSetup2DEngine()
325 		savage_out32(0x48C0C, 0, par);  in SavageSetup2DEngine()
327 		savage_out32(0x48C18, savage_in32(0x48C18, par) | 0x0C, par);  in SavageSetup2DEngine()
335 		savage_out32(0x48C18, savage_in32(0x48C18, par) & 0x3FF0, par);  in SavageSetup2DEngine()
337 		savage_out32(0x48C10, 0x00700040, par);  in SavageSetup2DEngine()
338 		savage_out32(0x48C0C, 0, par);  in SavageSetup2DEngine()
340 		savage_out32(0x48C18, savage_in32(0x48C18, par) | 0x08, par);  in SavageSetup2DEngine()
344 		savage_out32(0x48C18, 0, par);  in SavageSetup2DEngine()
346 		savage_out32(0x48C18,  in SavageSetup2DEngine()
350 		savage_out32(0x48A30, 0, par);  in SavageSetup2DEngine()
352 		savage_out32(0x48C18, savage_in32(0x48C18, par) | 0x00280000,  in SavageSetup2DEngine()
370 	savage_out32(MONO_PAT_0, ~0, par);  in SavageSetup2DEngine()
371 	savage_out32(MONO_PAT_1, ~0, par);  in SavageSetup2DEngine()
374 	savage_out32(0x8128, ~0, par); /* enable all write planes */  in SavageSetup2DEngine()
375 	savage_out32(0x812C, ~0, par); /* enable all read planes */  in SavageSetup2DEngine()
837 		savage_out32(FIFO_CONTROL_REG, reg->MMPR0, par);  in savage_set_default_par()
838 		savage_out32(MIU_CONTROL_REG, reg->MMPR1, par);  in savage_set_default_par()
839 		savage_out32(STREAMS_TIMEOUT_REG, reg->MMPR2, par);  in savage_set_default_par()
840 		savage_out32(MISC_TIMEOUT_REG, reg->MMPR3, par);  in savage_set_default_par()
1461 		savage_out32(FIFO_CONTROL_REG, reg->MMPR0, par);  in savagefb_set_par_int()
1463 		savage_out32(MIU_CONTROL_REG, reg->MMPR1, par);  in savagefb_set_par_int()
1465 		savage_out32(STREAMS_TIMEOUT_REG, reg->MMPR2, par);  in savagefb_set_par_int()
1467 		savage_out32(MISC_TIMEOUT_REG, reg->MMPR3, par);  in savagefb_set_par_int()