Lines Matching refs:vgabase
207 return vga_rcrt(par->state.vgabase, DDC_REG); in s3fb_ddc_read()
215 vga_wcrt(par->state.vgabase, DDC_REG, val); in s3fb_ddc_write()
286 svga_wseq_mask(par->state.vgabase, 0x0d, 0x01, 0x03); in s3fb_setup_ddc_bus()
288 svga_wseq_mask(par->state.vgabase, 0x0d, 0x00, 0x03); in s3fb_setup_ddc_bus()
290 svga_wcrt_mask(par->state.vgabase, 0x5c, 0x03, 0x03); in s3fb_setup_ddc_bus()
327 svga_tilecursor(par->state.vgabase, info, cursor); in s3fb_tilecursor()
484 regval = vga_r(par->state.vgabase, VGA_MIS_R); in s3_set_pixclock()
485 vga_w(par->state.vgabase, VGA_MIS_W, regval | VGA_MIS_ENB_PLL_LOAD); in s3_set_pixclock()
494 vga_wseq(par->state.vgabase, 0x12, (n - 2) | ((r & 3) << 6)); /* n and two bits of r */ in s3_set_pixclock()
495 vga_wseq(par->state.vgabase, 0x29, r >> 2); /* remaining highest bit of r */ in s3_set_pixclock()
497 vga_wseq(par->state.vgabase, 0x12, (n - 2) | (r << 5)); in s3_set_pixclock()
498 vga_wseq(par->state.vgabase, 0x13, m - 2); in s3_set_pixclock()
503 regval = vga_rseq (par->state.vgabase, 0x15); /* | 0x80; */ in s3_set_pixclock()
504 vga_wseq(par->state.vgabase, 0x15, regval & ~(1<<5)); in s3_set_pixclock()
505 vga_wseq(par->state.vgabase, 0x15, regval | (1<<5)); in s3_set_pixclock()
506 vga_wseq(par->state.vgabase, 0x15, regval & ~(1<<5)); in s3_set_pixclock()
518 void __iomem *vgabase = par->state.vgabase; in s3fb_open() local
521 par->state.vgabase = vgabase; in s3fb_open()
653 vga_wcrt(par->state.vgabase, 0x38, 0x48); in s3fb_set_par()
654 vga_wcrt(par->state.vgabase, 0x39, 0xA5); in s3fb_set_par()
655 vga_wseq(par->state.vgabase, 0x08, 0x06); in s3fb_set_par()
656 svga_wcrt_mask(par->state.vgabase, 0x11, 0x00, 0x80); in s3fb_set_par()
659 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20); in s3fb_set_par()
660 svga_wcrt_mask(par->state.vgabase, 0x17, 0x00, 0x80); in s3fb_set_par()
663 svga_set_default_gfx_regs(par->state.vgabase); in s3fb_set_par()
664 svga_set_default_atc_regs(par->state.vgabase); in s3fb_set_par()
665 svga_set_default_seq_regs(par->state.vgabase); in s3fb_set_par()
666 svga_set_default_crt_regs(par->state.vgabase); in s3fb_set_par()
667 svga_wcrt_multi(par->state.vgabase, s3_line_compare_regs, 0xFFFFFFFF); in s3fb_set_par()
668 svga_wcrt_multi(par->state.vgabase, s3_start_address_regs, 0); in s3fb_set_par()
671 svga_wcrt_mask(par->state.vgabase, 0x58, 0x10, 0x10); /* enable linear framebuffer */ in s3fb_set_par()
672 …svga_wcrt_mask(par->state.vgabase, 0x31, 0x08, 0x08); /* enable sequencer access to framebuffer ab… in s3fb_set_par()
676 svga_wcrt_mask(par->state.vgabase, 0x33, 0x00, 0x08); /* no DDR ? */ in s3fb_set_par()
677 svga_wcrt_mask(par->state.vgabase, 0x43, 0x00, 0x01); /* no DDR ? */ in s3fb_set_par()
679 svga_wcrt_mask(par->state.vgabase, 0x5D, 0x00, 0x28); /* Clear strange HSlen bits */ in s3fb_set_par()
689 svga_wcrt_multi(par->state.vgabase, s3_offset_regs, offset_value); in s3fb_set_par()
697 vga_wcrt(par->state.vgabase, 0x54, 0x18); /* M parameter */ in s3fb_set_par()
698 vga_wcrt(par->state.vgabase, 0x60, 0xff); /* N parameter */ in s3fb_set_par()
699 vga_wcrt(par->state.vgabase, 0x61, 0xff); /* L parameter */ in s3fb_set_par()
700 vga_wcrt(par->state.vgabase, 0x62, 0xff); /* L parameter */ in s3fb_set_par()
703 vga_wcrt(par->state.vgabase, 0x3A, 0x35); in s3fb_set_par()
704 svga_wattr(par->state.vgabase, 0x33, 0x00); in s3fb_set_par()
707 svga_wcrt_mask(par->state.vgabase, 0x09, 0x80, 0x80); in s3fb_set_par()
709 svga_wcrt_mask(par->state.vgabase, 0x09, 0x00, 0x80); in s3fb_set_par()
712 svga_wcrt_mask(par->state.vgabase, 0x42, 0x20, 0x20); in s3fb_set_par()
714 svga_wcrt_mask(par->state.vgabase, 0x42, 0x00, 0x20); in s3fb_set_par()
717 svga_wcrt_mask(par->state.vgabase, 0x45, 0x00, 0x01); in s3fb_set_par()
719 svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0x0C); in s3fb_set_par()
725 vga_wcrt(par->state.vgabase, 0x86, 0x80); in s3fb_set_par()
726 vga_wcrt(par->state.vgabase, 0x90, 0x00); in s3fb_set_par()
731 vga_wcrt(par->state.vgabase, 0x50, 0x00); in s3fb_set_par()
732 vga_wcrt(par->state.vgabase, 0x67, 0x50); in s3fb_set_par()
734 vga_wcrt(par->state.vgabase, 0x63, (mode <= 2) ? 0x90 : 0x09); in s3fb_set_par()
735 vga_wcrt(par->state.vgabase, 0x66, 0x90); in s3fb_set_par()
748 vga_wcrt(par->state.vgabase, 0x91, (dbytes + 7) / 8); in s3fb_set_par()
749 vga_wcrt(par->state.vgabase, 0x90, (((dbytes + 7) / 8) >> 8) | 0x80); in s3fb_set_par()
751 vga_wcrt(par->state.vgabase, 0x66, 0x81); in s3fb_set_par()
760 vga_wcrt(par->state.vgabase, 0x34, 0x00); in s3fb_set_par()
762 vga_wcrt(par->state.vgabase, 0x34, 0x10); in s3fb_set_par()
764 svga_wcrt_mask(par->state.vgabase, 0x31, 0x00, 0x40); in s3fb_set_par()
772 svga_set_textmode_vga_regs(par->state.vgabase); in s3fb_set_par()
775 svga_wcrt_mask(par->state.vgabase, 0x50, 0x00, 0x30); in s3fb_set_par()
776 svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0xF0); in s3fb_set_par()
779 svga_wcrt_mask(par->state.vgabase, 0x3A, 0x00, 0x30); in s3fb_set_par()
783 svga_wcrt_mask(par->state.vgabase, 0x31, 0x40, 0x40); in s3fb_set_par()
788 vga_wgfx(par->state.vgabase, VGA_GFX_MODE, 0x40); in s3fb_set_par()
791 svga_wcrt_mask(par->state.vgabase, 0x50, 0x00, 0x30); in s3fb_set_par()
792 svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0xF0); in s3fb_set_par()
795 svga_wcrt_mask(par->state.vgabase, 0x3A, 0x00, 0x30); in s3fb_set_par()
801 svga_wcrt_mask(par->state.vgabase, 0x50, 0x00, 0x30); in s3fb_set_par()
802 svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0xF0); in s3fb_set_par()
805 svga_wcrt_mask(par->state.vgabase, 0x3A, 0x00, 0x30); in s3fb_set_par()
809 svga_wcrt_mask(par->state.vgabase, 0x50, 0x00, 0x30); in s3fb_set_par()
817 svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0xF0); in s3fb_set_par()
819 svga_wcrt_mask(par->state.vgabase, 0x67, 0x10, 0xF0); in s3fb_set_par()
827 svga_wcrt_mask(par->state.vgabase, 0x67, 0x20, 0xF0); in s3fb_set_par()
829 svga_wcrt_mask(par->state.vgabase, 0x67, 0x30, 0xF0); in s3fb_set_par()
831 svga_wcrt_mask(par->state.vgabase, 0x50, 0x10, 0x30); in s3fb_set_par()
833 svga_wcrt_mask(par->state.vgabase, 0x67, 0x30, 0xF0); in s3fb_set_par()
836 svga_wcrt_mask(par->state.vgabase, 0x67, 0x20, 0xF0); in s3fb_set_par()
840 svga_wcrt_mask(par->state.vgabase, 0x50, 0x10, 0x30); in s3fb_set_par()
841 svga_wcrt_mask(par->state.vgabase, 0x67, 0x30, 0xF0); in s3fb_set_par()
855 svga_wcrt_mask(par->state.vgabase, 0x67, 0x40, 0xF0); in s3fb_set_par()
857 svga_wcrt_mask(par->state.vgabase, 0x67, 0x50, 0xF0); in s3fb_set_par()
859 svga_wcrt_mask(par->state.vgabase, 0x50, 0x10, 0x30); in s3fb_set_par()
861 svga_wcrt_mask(par->state.vgabase, 0x67, 0x50, 0xF0); in s3fb_set_par()
864 svga_wcrt_mask(par->state.vgabase, 0x67, 0x40, 0xF0); in s3fb_set_par()
868 svga_wcrt_mask(par->state.vgabase, 0x50, 0x10, 0x30); in s3fb_set_par()
869 svga_wcrt_mask(par->state.vgabase, 0x67, 0x50, 0xF0); in s3fb_set_par()
882 svga_wcrt_mask(par->state.vgabase, 0x67, 0xD0, 0xF0); in s3fb_set_par()
886 svga_wcrt_mask(par->state.vgabase, 0x50, 0x30, 0x30); in s3fb_set_par()
887 svga_wcrt_mask(par->state.vgabase, 0x67, 0xD0, 0xF0); in s3fb_set_par()
895 svga_wseq_mask(par->state.vgabase, 0x15, multiplex ? 0x10 : 0x00, 0x10); in s3fb_set_par()
896 svga_wseq_mask(par->state.vgabase, 0x18, multiplex ? 0x80 : 0x00, 0x80); in s3fb_set_par()
900 svga_set_timings(par->state.vgabase, &s3_timing_regs, &(info->var), hmul, 1, in s3fb_set_par()
908 vga_wcrt(par->state.vgabase, 0x3C, (htotal + 1) / 2); in s3fb_set_par()
914 svga_wcrt_multi(par->state.vgabase, s3_dtpc_regs, value); in s3fb_set_par()
918 svga_wcrt_mask(par->state.vgabase, 0x17, 0x80, 0x80); in s3fb_set_par()
919 svga_wseq_mask(par->state.vgabase, 0x01, 0x00, 0x20); in s3fb_set_par()
994 svga_wcrt_mask(par->state.vgabase, 0x56, 0x00, 0x06); in s3fb_blank()
995 svga_wseq_mask(par->state.vgabase, 0x01, 0x00, 0x20); in s3fb_blank()
999 svga_wcrt_mask(par->state.vgabase, 0x56, 0x00, 0x06); in s3fb_blank()
1000 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20); in s3fb_blank()
1004 svga_wcrt_mask(par->state.vgabase, 0x56, 0x02, 0x06); in s3fb_blank()
1005 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20); in s3fb_blank()
1009 svga_wcrt_mask(par->state.vgabase, 0x56, 0x04, 0x06); in s3fb_blank()
1010 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20); in s3fb_blank()
1014 svga_wcrt_mask(par->state.vgabase, 0x56, 0x06, 0x06); in s3fb_blank()
1015 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20); in s3fb_blank()
1042 svga_wcrt_multi(par->state.vgabase, s3_start_address_regs, offset); in s3fb_pan_display()
1073 u8 cr30 = vga_rcrt(par->state.vgabase, 0x30); in s3_identification()
1074 u8 cr2e = vga_rcrt(par->state.vgabase, 0x2e); in s3_identification()
1075 u8 cr2f = vga_rcrt(par->state.vgabase, 0x2f); in s3_identification()
1090 u8 cr6f = vga_rcrt(par->state.vgabase, 0x6f); in s3_identification()
1099 u8 cr6f = vga_rcrt(par->state.vgabase, 0x6f); in s3_identification()
1108 switch (vga_rcrt(par->state.vgabase, 0x2f)) { in s3_identification()
1185 par->state.vgabase = (void __iomem *) (unsigned long) vga_res.start; in s3_pci_probe()
1188 cr38 = vga_rcrt(par->state.vgabase, 0x38); in s3_pci_probe()
1189 cr39 = vga_rcrt(par->state.vgabase, 0x39); in s3_pci_probe()
1190 vga_wseq(par->state.vgabase, 0x08, 0x06); in s3_pci_probe()
1191 vga_wcrt(par->state.vgabase, 0x38, 0x48); in s3_pci_probe()
1192 vga_wcrt(par->state.vgabase, 0x39, 0xA5); in s3_pci_probe()
1196 par->rev = vga_rcrt(par->state.vgabase, 0x2f); in s3_pci_probe()
1202 regval = vga_rcrt(par->state.vgabase, 0x36); in s3_pci_probe()
1245 regval = vga_rcrt(par->state.vgabase, 0x37); in s3_pci_probe()
1259 regval = vga_rseq(par->state.vgabase, 0x10); in s3_pci_probe()
1260 par->mclk_freq = ((vga_rseq(par->state.vgabase, 0x11) + 2) * 14318) / ((regval & 0x1F) + 2); in s3_pci_probe()
1264 vga_wcrt(par->state.vgabase, 0x38, cr38); in s3_pci_probe()
1265 vga_wcrt(par->state.vgabase, 0x39, cr39); in s3_pci_probe()
1282 svga_wcrt_mask(par->state.vgabase, 0x53, 0x08, 0x08); /* enable MMIO */ in s3_pci_probe()
1360 vga_rcrt(par->state.vgabase, 0x2d), in s3_pci_probe()
1361 vga_rcrt(par->state.vgabase, 0x2e), in s3_pci_probe()
1362 vga_rcrt(par->state.vgabase, 0x2f), in s3_pci_probe()
1363 vga_rcrt(par->state.vgabase, 0x30)); in s3_pci_probe()