202 static u8 s3fb_ddc_read(struct s3fb_info *par)  in s3fb_ddc_read()  argument
204 	if (s3fb_ddc_needs_mmio(par->chip))  in s3fb_ddc_read()
205 		return readb(par->mmio + DDC_MMIO_REG);  in s3fb_ddc_read()
207 		return vga_rcrt(par->state.vgabase, DDC_REG);  in s3fb_ddc_read()
210 static void s3fb_ddc_write(struct s3fb_info *par, u8 val)  in s3fb_ddc_write()  argument
212 	if (s3fb_ddc_needs_mmio(par->chip))  in s3fb_ddc_write()
213 		writeb(val, par->mmio + DDC_MMIO_REG);  in s3fb_ddc_write()
215 		vga_wcrt(par->state.vgabase, DDC_REG, val);  in s3fb_ddc_write()
220 	struct s3fb_info *par = data;  in s3fb_ddc_setscl()  local
223 	reg = s3fb_ddc_read(par) | DDC_DRIVE_EN;  in s3fb_ddc_setscl()
228 	s3fb_ddc_write(par, reg);  in s3fb_ddc_setscl()
233 	struct s3fb_info *par = data;  in s3fb_ddc_setsda()  local
236 	reg = s3fb_ddc_read(par) | DDC_DRIVE_EN;  in s3fb_ddc_setsda()
241 	s3fb_ddc_write(par, reg);  in s3fb_ddc_setsda()
246 	struct s3fb_info *par = data;  in s3fb_ddc_getscl()  local
248 	return !!(s3fb_ddc_read(par) & DDC_SCL_IN);  in s3fb_ddc_getscl()
253 	struct s3fb_info *par = data;  in s3fb_ddc_getsda()  local
255 	return !!(s3fb_ddc_read(par) & DDC_SDA_IN);  in s3fb_ddc_getsda()
260 	struct s3fb_info *par = info->par;  in s3fb_setup_ddc_bus()  local
262 	strlcpy(par->ddc_adapter.name, info->fix.id,  in s3fb_setup_ddc_bus()
263 		sizeof(par->ddc_adapter.name));  in s3fb_setup_ddc_bus()
264 	par->ddc_adapter.owner		= THIS_MODULE;  in s3fb_setup_ddc_bus()
265 	par->ddc_adapter.class		= I2C_CLASS_DDC;  in s3fb_setup_ddc_bus()
266 	par->ddc_adapter.algo_data	= &par->ddc_algo;  in s3fb_setup_ddc_bus()
267 	par->ddc_adapter.dev.parent	= info->device;  in s3fb_setup_ddc_bus()
268 	par->ddc_algo.setsda		= s3fb_ddc_setsda;  in s3fb_setup_ddc_bus()
269 	par->ddc_algo.setscl		= s3fb_ddc_setscl;  in s3fb_setup_ddc_bus()
270 	par->ddc_algo.getsda		= s3fb_ddc_getsda;  in s3fb_setup_ddc_bus()
271 	par->ddc_algo.getscl		= s3fb_ddc_getscl;  in s3fb_setup_ddc_bus()
272 	par->ddc_algo.udelay		= 10;  in s3fb_setup_ddc_bus()
273 	par->ddc_algo.timeout		= 20;  in s3fb_setup_ddc_bus()
274 	par->ddc_algo.data		= par;  in s3fb_setup_ddc_bus()
276 	i2c_set_adapdata(&par->ddc_adapter, par);  in s3fb_setup_ddc_bus()
283 	if (par->chip == CHIP_357_VIRGE_GX2 ||  in s3fb_setup_ddc_bus()
284 	    par->chip == CHIP_359_VIRGE_GX2P ||  in s3fb_setup_ddc_bus()
285 	    par->chip == CHIP_260_VIRGE_MX)  in s3fb_setup_ddc_bus()
286 		svga_wseq_mask(par->state.vgabase, 0x0d, 0x01, 0x03);  in s3fb_setup_ddc_bus()
288 		svga_wseq_mask(par->state.vgabase, 0x0d, 0x00, 0x03);  in s3fb_setup_ddc_bus()
290 	svga_wcrt_mask(par->state.vgabase, 0x5c, 0x03, 0x03);  in s3fb_setup_ddc_bus()
292 	return i2c_bit_add_bus(&par->ddc_adapter);  in s3fb_setup_ddc_bus()
325 	struct s3fb_info *par = info->par;  in s3fb_tilecursor()  local
327 	svga_tilecursor(par->state.vgabase, info, cursor);  in s3fb_tilecursor()
471 	struct s3fb_info *par = info->par;  in s3_set_pixclock()  local
476 	rv = svga_compute_pll((par->chip == CHIP_365_TRIO3D) ? &s3_trio3d_pll : &s3_pll,  in s3_set_pixclock()
484 	regval = vga_r(par->state.vgabase, VGA_MIS_R);  in s3_set_pixclock()
485 	vga_w(par->state.vgabase, VGA_MIS_W, regval | VGA_MIS_ENB_PLL_LOAD);  in s3_set_pixclock()
488 	if (par->chip == CHIP_357_VIRGE_GX2 ||  in s3_set_pixclock()
489 	    par->chip == CHIP_359_VIRGE_GX2P ||  in s3_set_pixclock()
490 	    par->chip == CHIP_360_TRIO3D_1X ||  in s3_set_pixclock()
491 	    par->chip == CHIP_362_TRIO3D_2X ||  in s3_set_pixclock()
492 	    par->chip == CHIP_368_TRIO3D_2X ||  in s3_set_pixclock()
493 	    par->chip == CHIP_260_VIRGE_MX) {  in s3_set_pixclock()
494 		vga_wseq(par->state.vgabase, 0x12, (n - 2) | ((r & 3) << 6));	/* n and two bits of r */  in s3_set_pixclock()
495 		vga_wseq(par->state.vgabase, 0x29, r >> 2); /* remaining highest bit of r */  in s3_set_pixclock()
497 		vga_wseq(par->state.vgabase, 0x12, (n - 2) | (r << 5));  in s3_set_pixclock()
498 	vga_wseq(par->state.vgabase, 0x13, m - 2);  in s3_set_pixclock()
503 	regval = vga_rseq (par->state.vgabase, 0x15); /* | 0x80; */  in s3_set_pixclock()
504 	vga_wseq(par->state.vgabase, 0x15, regval & ~(1<<5));  in s3_set_pixclock()
505 	vga_wseq(par->state.vgabase, 0x15, regval |  (1<<5));  in s3_set_pixclock()
506 	vga_wseq(par->state.vgabase, 0x15, regval & ~(1<<5));  in s3_set_pixclock()
514 	struct s3fb_info *par = info->par;  in s3fb_open()  local
516 	mutex_lock(&(par->open_lock));  in s3fb_open()
517 	if (par->ref_count == 0) {  in s3fb_open()
518 		void __iomem *vgabase = par->state.vgabase;  in s3fb_open()
520 		memset(&(par->state), 0, sizeof(struct vgastate));  in s3fb_open()
521 		par->state.vgabase = vgabase;  in s3fb_open()
522 		par->state.flags = VGA_SAVE_MODE | VGA_SAVE_FONTS | VGA_SAVE_CMAP;  in s3fb_open()
523 		par->state.num_crtc = 0x70;  in s3fb_open()
524 		par->state.num_seq = 0x20;  in s3fb_open()
525 		save_vga(&(par->state));  in s3fb_open()
528 	par->ref_count++;  in s3fb_open()
529 	mutex_unlock(&(par->open_lock));  in s3fb_open()
538 	struct s3fb_info *par = info->par;  in s3fb_release()  local
540 	mutex_lock(&(par->open_lock));  in s3fb_release()
541 	if (par->ref_count == 0) {  in s3fb_release()
542 		mutex_unlock(&(par->open_lock));  in s3fb_release()
546 	if (par->ref_count == 1)  in s3fb_release()
547 		restore_vga(&(par->state));  in s3fb_release()
549 	par->ref_count--;  in s3fb_release()
550 	mutex_unlock(&(par->open_lock));  in s3fb_release()
559 	struct s3fb_info *par = info->par;  in s3fb_check_var()  local
568 	if ((par->chip == CHIP_988_VIRGE_VX) ? (rv == 7) : (rv == 6))  in s3fb_check_var()
615 	struct s3fb_info *par = info->par;  in s3fb_set_par()  local
653 	vga_wcrt(par->state.vgabase, 0x38, 0x48);  in s3fb_set_par()
654 	vga_wcrt(par->state.vgabase, 0x39, 0xA5);  in s3fb_set_par()
655 	vga_wseq(par->state.vgabase, 0x08, 0x06);  in s3fb_set_par()
656 	svga_wcrt_mask(par->state.vgabase, 0x11, 0x00, 0x80);  in s3fb_set_par()
659 	svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);  in s3fb_set_par()
660 	svga_wcrt_mask(par->state.vgabase, 0x17, 0x00, 0x80);  in s3fb_set_par()
663 	svga_set_default_gfx_regs(par->state.vgabase);  in s3fb_set_par()
664 	svga_set_default_atc_regs(par->state.vgabase);  in s3fb_set_par()
665 	svga_set_default_seq_regs(par->state.vgabase);  in s3fb_set_par()
666 	svga_set_default_crt_regs(par->state.vgabase);  in s3fb_set_par()
667 	svga_wcrt_multi(par->state.vgabase, s3_line_compare_regs, 0xFFFFFFFF);  in s3fb_set_par()
668 	svga_wcrt_multi(par->state.vgabase, s3_start_address_regs, 0);  in s3fb_set_par()
671 	svga_wcrt_mask(par->state.vgabase, 0x58, 0x10, 0x10); /* enable linear framebuffer */  in s3fb_set_par()
672 …svga_wcrt_mask(par->state.vgabase, 0x31, 0x08, 0x08); /* enable sequencer access to framebuffer ab…  in s3fb_set_par()
676 	svga_wcrt_mask(par->state.vgabase, 0x33, 0x00, 0x08); /* no DDR ?	*/  in s3fb_set_par()
677 	svga_wcrt_mask(par->state.vgabase, 0x43, 0x00, 0x01); /* no DDR ?	*/  in s3fb_set_par()
679 	svga_wcrt_mask(par->state.vgabase, 0x5D, 0x00, 0x28); /* Clear strange HSlen bits */  in s3fb_set_par()
689 	svga_wcrt_multi(par->state.vgabase, s3_offset_regs, offset_value);  in s3fb_set_par()
691 	if (par->chip != CHIP_357_VIRGE_GX2 &&  in s3fb_set_par()
692 	    par->chip != CHIP_359_VIRGE_GX2P &&  in s3fb_set_par()
693 	    par->chip != CHIP_360_TRIO3D_1X &&  in s3fb_set_par()
694 	    par->chip != CHIP_362_TRIO3D_2X &&  in s3fb_set_par()
695 	    par->chip != CHIP_368_TRIO3D_2X &&  in s3fb_set_par()
696 	    par->chip != CHIP_260_VIRGE_MX) {  in s3fb_set_par()
697 		vga_wcrt(par->state.vgabase, 0x54, 0x18); /* M parameter */  in s3fb_set_par()
698 		vga_wcrt(par->state.vgabase, 0x60, 0xff); /* N parameter */  in s3fb_set_par()
699 		vga_wcrt(par->state.vgabase, 0x61, 0xff); /* L parameter */  in s3fb_set_par()
700 		vga_wcrt(par->state.vgabase, 0x62, 0xff); /* L parameter */  in s3fb_set_par()
703 	vga_wcrt(par->state.vgabase, 0x3A, 0x35);  in s3fb_set_par()
704 	svga_wattr(par->state.vgabase, 0x33, 0x00);  in s3fb_set_par()
707 		svga_wcrt_mask(par->state.vgabase, 0x09, 0x80, 0x80);  in s3fb_set_par()
709 		svga_wcrt_mask(par->state.vgabase, 0x09, 0x00, 0x80);  in s3fb_set_par()
712 		svga_wcrt_mask(par->state.vgabase, 0x42, 0x20, 0x20);  in s3fb_set_par()
714 		svga_wcrt_mask(par->state.vgabase, 0x42, 0x00, 0x20);  in s3fb_set_par()
717 	svga_wcrt_mask(par->state.vgabase, 0x45, 0x00, 0x01);  in s3fb_set_par()
719 	svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0x0C);  in s3fb_set_par()
724 	if (par->chip == CHIP_375_VIRGE_DX) {  in s3fb_set_par()
725 		vga_wcrt(par->state.vgabase, 0x86, 0x80);  in s3fb_set_par()
726 		vga_wcrt(par->state.vgabase, 0x90, 0x00);  in s3fb_set_par()
730 	if (par->chip == CHIP_988_VIRGE_VX) {  in s3fb_set_par()
731 		vga_wcrt(par->state.vgabase, 0x50, 0x00);  in s3fb_set_par()
732 		vga_wcrt(par->state.vgabase, 0x67, 0x50);  in s3fb_set_par()
734 		vga_wcrt(par->state.vgabase, 0x63, (mode <= 2) ? 0x90 : 0x09);  in s3fb_set_par()
735 		vga_wcrt(par->state.vgabase, 0x66, 0x90);  in s3fb_set_par()
738 	if (par->chip == CHIP_357_VIRGE_GX2 ||  in s3fb_set_par()
739 	    par->chip == CHIP_359_VIRGE_GX2P ||  in s3fb_set_par()
740 	    par->chip == CHIP_360_TRIO3D_1X ||  in s3fb_set_par()
741 	    par->chip == CHIP_362_TRIO3D_2X ||  in s3fb_set_par()
742 	    par->chip == CHIP_368_TRIO3D_2X ||  in s3fb_set_par()
743 	    par->chip == CHIP_365_TRIO3D    ||  in s3fb_set_par()
744 	    par->chip == CHIP_375_VIRGE_DX  ||  in s3fb_set_par()
745 	    par->chip == CHIP_385_VIRGE_GX  ||  in s3fb_set_par()
746 	    par->chip == CHIP_260_VIRGE_MX) {  in s3fb_set_par()
748 		vga_wcrt(par->state.vgabase, 0x91, (dbytes + 7) / 8);  in s3fb_set_par()
749 		vga_wcrt(par->state.vgabase, 0x90, (((dbytes + 7) / 8) >> 8) | 0x80);  in s3fb_set_par()
751 		vga_wcrt(par->state.vgabase, 0x66, 0x81);  in s3fb_set_par()
754 	if (par->chip == CHIP_357_VIRGE_GX2  ||  in s3fb_set_par()
755 	    par->chip == CHIP_359_VIRGE_GX2P ||  in s3fb_set_par()
756 	    par->chip == CHIP_360_TRIO3D_1X ||  in s3fb_set_par()
757 	    par->chip == CHIP_362_TRIO3D_2X ||  in s3fb_set_par()
758 	    par->chip == CHIP_368_TRIO3D_2X ||  in s3fb_set_par()
759 	    par->chip == CHIP_260_VIRGE_MX)  in s3fb_set_par()
760 		vga_wcrt(par->state.vgabase, 0x34, 0x00);  in s3fb_set_par()
762 		vga_wcrt(par->state.vgabase, 0x34, 0x10);  in s3fb_set_par()
764 	svga_wcrt_mask(par->state.vgabase, 0x31, 0x00, 0x40);  in s3fb_set_par()
772 		svga_set_textmode_vga_regs(par->state.vgabase);  in s3fb_set_par()
775 		svga_wcrt_mask(par->state.vgabase, 0x50, 0x00, 0x30);  in s3fb_set_par()
776 		svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0xF0);  in s3fb_set_par()
779 		svga_wcrt_mask(par->state.vgabase, 0x3A, 0x00, 0x30);  in s3fb_set_par()
783 			svga_wcrt_mask(par->state.vgabase, 0x31, 0x40, 0x40);  in s3fb_set_par()
788 		vga_wgfx(par->state.vgabase, VGA_GFX_MODE, 0x40);  in s3fb_set_par()
791 		svga_wcrt_mask(par->state.vgabase, 0x50, 0x00, 0x30);  in s3fb_set_par()
792 		svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0xF0);  in s3fb_set_par()
795 		svga_wcrt_mask(par->state.vgabase, 0x3A, 0x00, 0x30);  in s3fb_set_par()
801 		svga_wcrt_mask(par->state.vgabase, 0x50, 0x00, 0x30);  in s3fb_set_par()
802 		svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0xF0);  in s3fb_set_par()
805 		svga_wcrt_mask(par->state.vgabase, 0x3A, 0x00, 0x30);  in s3fb_set_par()
809 		svga_wcrt_mask(par->state.vgabase, 0x50, 0x00, 0x30);  in s3fb_set_par()
811 		    par->chip == CHIP_357_VIRGE_GX2 ||  in s3fb_set_par()
812 		    par->chip == CHIP_359_VIRGE_GX2P ||  in s3fb_set_par()
813 		    par->chip == CHIP_360_TRIO3D_1X ||  in s3fb_set_par()
814 		    par->chip == CHIP_362_TRIO3D_2X ||  in s3fb_set_par()
815 		    par->chip == CHIP_368_TRIO3D_2X ||  in s3fb_set_par()
816 		    par->chip == CHIP_260_VIRGE_MX)  in s3fb_set_par()
817 			svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0xF0);  in s3fb_set_par()
819 			svga_wcrt_mask(par->state.vgabase, 0x67, 0x10, 0xF0);  in s3fb_set_par()
825 		if (par->chip == CHIP_988_VIRGE_VX) {  in s3fb_set_par()
827 				svga_wcrt_mask(par->state.vgabase, 0x67, 0x20, 0xF0);  in s3fb_set_par()
829 				svga_wcrt_mask(par->state.vgabase, 0x67, 0x30, 0xF0);  in s3fb_set_par()
830 		} else if (par->chip == CHIP_365_TRIO3D) {  in s3fb_set_par()
831 			svga_wcrt_mask(par->state.vgabase, 0x50, 0x10, 0x30);  in s3fb_set_par()
833 				svga_wcrt_mask(par->state.vgabase, 0x67, 0x30, 0xF0);  in s3fb_set_par()
836 				svga_wcrt_mask(par->state.vgabase, 0x67, 0x20, 0xF0);  in s3fb_set_par()
840 			svga_wcrt_mask(par->state.vgabase, 0x50, 0x10, 0x30);  in s3fb_set_par()
841 			svga_wcrt_mask(par->state.vgabase, 0x67, 0x30, 0xF0);  in s3fb_set_par()
842 			if (par->chip != CHIP_357_VIRGE_GX2 &&  in s3fb_set_par()
843 			    par->chip != CHIP_359_VIRGE_GX2P &&  in s3fb_set_par()
844 			    par->chip != CHIP_360_TRIO3D_1X &&  in s3fb_set_par()
845 			    par->chip != CHIP_362_TRIO3D_2X &&  in s3fb_set_par()
846 			    par->chip != CHIP_368_TRIO3D_2X &&  in s3fb_set_par()
847 			    par->chip != CHIP_260_VIRGE_MX)  in s3fb_set_par()
853 		if (par->chip == CHIP_988_VIRGE_VX) {  in s3fb_set_par()
855 				svga_wcrt_mask(par->state.vgabase, 0x67, 0x40, 0xF0);  in s3fb_set_par()
857 				svga_wcrt_mask(par->state.vgabase, 0x67, 0x50, 0xF0);  in s3fb_set_par()
858 		} else if (par->chip == CHIP_365_TRIO3D) {  in s3fb_set_par()
859 			svga_wcrt_mask(par->state.vgabase, 0x50, 0x10, 0x30);  in s3fb_set_par()
861 				svga_wcrt_mask(par->state.vgabase, 0x67, 0x50, 0xF0);  in s3fb_set_par()
864 				svga_wcrt_mask(par->state.vgabase, 0x67, 0x40, 0xF0);  in s3fb_set_par()
868 			svga_wcrt_mask(par->state.vgabase, 0x50, 0x10, 0x30);  in s3fb_set_par()
869 			svga_wcrt_mask(par->state.vgabase, 0x67, 0x50, 0xF0);  in s3fb_set_par()
870 			if (par->chip != CHIP_357_VIRGE_GX2 &&  in s3fb_set_par()
871 			    par->chip != CHIP_359_VIRGE_GX2P &&  in s3fb_set_par()
872 			    par->chip != CHIP_360_TRIO3D_1X &&  in s3fb_set_par()
873 			    par->chip != CHIP_362_TRIO3D_2X &&  in s3fb_set_par()
874 			    par->chip != CHIP_368_TRIO3D_2X &&  in s3fb_set_par()
875 			    par->chip != CHIP_260_VIRGE_MX)  in s3fb_set_par()
882 		svga_wcrt_mask(par->state.vgabase, 0x67, 0xD0, 0xF0);  in s3fb_set_par()
886 		svga_wcrt_mask(par->state.vgabase, 0x50, 0x30, 0x30);  in s3fb_set_par()
887 		svga_wcrt_mask(par->state.vgabase, 0x67, 0xD0, 0xF0);  in s3fb_set_par()
894 	if (par->chip != CHIP_988_VIRGE_VX) {  in s3fb_set_par()
895 		svga_wseq_mask(par->state.vgabase, 0x15, multiplex ? 0x10 : 0x00, 0x10);  in s3fb_set_par()
896 		svga_wseq_mask(par->state.vgabase, 0x18, multiplex ? 0x80 : 0x00, 0x80);  in s3fb_set_par()
900 	svga_set_timings(par->state.vgabase, &s3_timing_regs, &(info->var), hmul, 1,  in s3fb_set_par()
908 	vga_wcrt(par->state.vgabase, 0x3C, (htotal + 1) / 2);  in s3fb_set_par()
914 	svga_wcrt_multi(par->state.vgabase, s3_dtpc_regs, value);  in s3fb_set_par()
918 	svga_wcrt_mask(par->state.vgabase, 0x17, 0x80, 0x80);  in s3fb_set_par()
919 	svga_wseq_mask(par->state.vgabase, 0x01, 0x00, 0x20);  in s3fb_set_par()
989 	struct s3fb_info *par = info->par;  in s3fb_blank()  local
994 		svga_wcrt_mask(par->state.vgabase, 0x56, 0x00, 0x06);  in s3fb_blank()
995 		svga_wseq_mask(par->state.vgabase, 0x01, 0x00, 0x20);  in s3fb_blank()
999 		svga_wcrt_mask(par->state.vgabase, 0x56, 0x00, 0x06);  in s3fb_blank()
1000 		svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);  in s3fb_blank()
1004 		svga_wcrt_mask(par->state.vgabase, 0x56, 0x02, 0x06);  in s3fb_blank()
1005 		svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);  in s3fb_blank()
1009 		svga_wcrt_mask(par->state.vgabase, 0x56, 0x04, 0x06);  in s3fb_blank()
1010 		svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);  in s3fb_blank()
1014 		svga_wcrt_mask(par->state.vgabase, 0x56, 0x06, 0x06);  in s3fb_blank()
1015 		svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);  in s3fb_blank()
1027 	struct s3fb_info *par = info->par;  in s3fb_pan_display()  local
1042 	svga_wcrt_multi(par->state.vgabase, s3_start_address_regs, offset);  in s3fb_pan_display()
1068 static int s3_identification(struct s3fb_info *par)  in s3_identification()  argument
1070 	int chip = par->chip;  in s3_identification()
1073 		u8 cr30 = vga_rcrt(par->state.vgabase, 0x30);  in s3_identification()
1074 		u8 cr2e = vga_rcrt(par->state.vgabase, 0x2e);  in s3_identification()
1075 		u8 cr2f = vga_rcrt(par->state.vgabase, 0x2f);  in s3_identification()
1090 		u8 cr6f = vga_rcrt(par->state.vgabase, 0x6f);  in s3_identification()
1099 		u8 cr6f = vga_rcrt(par->state.vgabase, 0x6f);  in s3_identification()
1108 		switch (vga_rcrt(par->state.vgabase, 0x2f)) {  in s3_identification()
1129 	struct s3fb_info *par;  in s3_pci_probe()  local
1147 	par = info->par;  in s3_pci_probe()
1148 	mutex_init(&par->open_lock);  in s3_pci_probe()
1185 	par->state.vgabase = (void __iomem *) (unsigned long) vga_res.start;  in s3_pci_probe()
1188 	cr38 = vga_rcrt(par->state.vgabase, 0x38);  in s3_pci_probe()
1189 	cr39 = vga_rcrt(par->state.vgabase, 0x39);  in s3_pci_probe()
1190 	vga_wseq(par->state.vgabase, 0x08, 0x06);  in s3_pci_probe()
1191 	vga_wcrt(par->state.vgabase, 0x38, 0x48);  in s3_pci_probe()
1192 	vga_wcrt(par->state.vgabase, 0x39, 0xA5);  in s3_pci_probe()
1195 	par->chip = id->driver_data & CHIP_MASK;  in s3_pci_probe()
1196 	par->rev = vga_rcrt(par->state.vgabase, 0x2f);  in s3_pci_probe()
1197 	if (par->chip & CHIP_UNDECIDED_FLAG)  in s3_pci_probe()
1198 		par->chip = s3_identification(par);  in s3_pci_probe()
1202 	regval = vga_rcrt(par->state.vgabase, 0x36);  in s3_pci_probe()
1203 	if (par->chip == CHIP_360_TRIO3D_1X ||  in s3_pci_probe()
1204 	    par->chip == CHIP_362_TRIO3D_2X ||  in s3_pci_probe()
1205 	    par->chip == CHIP_368_TRIO3D_2X ||  in s3_pci_probe()
1206 	    par->chip == CHIP_365_TRIO3D) {  in s3_pci_probe()
1218 	} else if (par->chip == CHIP_357_VIRGE_GX2 ||  in s3_pci_probe()
1219 		   par->chip == CHIP_359_VIRGE_GX2P ||  in s3_pci_probe()
1220 		   par->chip == CHIP_260_VIRGE_MX) {  in s3_pci_probe()
1229 	} else if (par->chip == CHIP_988_VIRGE_VX) {  in s3_pci_probe()
1245 		regval = vga_rcrt(par->state.vgabase, 0x37);  in s3_pci_probe()
1259 	regval = vga_rseq(par->state.vgabase, 0x10);  in s3_pci_probe()
1260 	par->mclk_freq = ((vga_rseq(par->state.vgabase, 0x11) + 2) * 14318) / ((regval & 0x1F)  + 2);  in s3_pci_probe()
1261 	par->mclk_freq = par->mclk_freq >> (regval >> 5);  in s3_pci_probe()
1264 	vga_wcrt(par->state.vgabase, 0x38, cr38);  in s3_pci_probe()
1265 	vga_wcrt(par->state.vgabase, 0x39, cr39);  in s3_pci_probe()
1267 	strcpy(info->fix.id, s3_names [par->chip]);  in s3_pci_probe()
1274 	info->pseudo_palette = (void*) (par->pseudo_palette);  in s3_pci_probe()
1279 	if (s3fb_ddc_needs_mmio(par->chip)) {  in s3_pci_probe()
1280 		par->mmio = ioremap(info->fix.smem_start + MMIO_OFFSET, MMIO_SIZE);  in s3_pci_probe()
1281 		if (par->mmio)  in s3_pci_probe()
1282 			svga_wcrt_mask(par->state.vgabase, 0x53, 0x08, 0x08);	/* enable MMIO */  in s3_pci_probe()
1287 	if (!s3fb_ddc_needs_mmio(par->chip) || par->mmio)  in s3_pci_probe()
1289 			u8 *edid = fb_ddc_read(&par->ddc_adapter);  in s3_pci_probe()
1290 			par->ddc_registered = true;  in s3_pci_probe()
1356 		info->fix.smem_len >> 20, (par->mclk_freq + 500) / 1000);  in s3_pci_probe()
1358 	if (par->chip == CHIP_UNKNOWN)  in s3_pci_probe()
1360 			vga_rcrt(par->state.vgabase, 0x2d),  in s3_pci_probe()
1361 			vga_rcrt(par->state.vgabase, 0x2e),  in s3_pci_probe()
1362 			vga_rcrt(par->state.vgabase, 0x2f),  in s3_pci_probe()
1363 			vga_rcrt(par->state.vgabase, 0x30));  in s3_pci_probe()
1370 		par->mtrr_reg = -1;  in s3_pci_probe()
1371 		par->mtrr_reg = mtrr_add(info->fix.smem_start, info->fix.smem_len, MTRR_TYPE_WRCOMB, 1);  in s3_pci_probe()
1383 	if (par->ddc_registered)  in s3_pci_probe()
1384 		i2c_del_adapter(&par->ddc_adapter);  in s3_pci_probe()
1385 	if (par->mmio)  in s3_pci_probe()
1386 		iounmap(par->mmio);  in s3_pci_probe()
1404 	struct s3fb_info __maybe_unused *par;  in s3_pci_remove()  local
1407 		par = info->par;  in s3_pci_remove()
1410 		if (par->mtrr_reg >= 0) {  in s3_pci_remove()
1411 			mtrr_del(par->mtrr_reg, 0, 0);  in s3_pci_remove()
1412 			par->mtrr_reg = -1;  in s3_pci_remove()
1420 		if (par->ddc_registered)  in s3_pci_remove()
1421 			i2c_del_adapter(&par->ddc_adapter);  in s3_pci_remove()
1422 		if (par->mmio)  in s3_pci_remove()
1423 			iounmap(par->mmio);  in s3_pci_remove()
1439 	struct s3fb_info *par = info->par;  in s3_pci_suspend()  local
1444 	mutex_lock(&(par->open_lock));  in s3_pci_suspend()
1446 	if ((state.event == PM_EVENT_FREEZE) || (par->ref_count == 0)) {  in s3_pci_suspend()
1447 		mutex_unlock(&(par->open_lock));  in s3_pci_suspend()
1458 	mutex_unlock(&(par->open_lock));  in s3_pci_suspend()
1470 	struct s3fb_info *par = info->par;  in s3_pci_resume()  local
1476 	mutex_lock(&(par->open_lock));  in s3_pci_resume()
1478 	if (par->ref_count == 0) {  in s3_pci_resume()
1479 		mutex_unlock(&(par->open_lock));  in s3_pci_resume()
1488 		mutex_unlock(&(par->open_lock));  in s3_pci_resume()
1498 	mutex_unlock(&(par->open_lock));  in s3_pci_resume()