29 void hdmi_phy_dump(struct hdmi_phy_data *phy, struct seq_file *s)  in hdmi_phy_dump()  argument
32 		hdmi_read_reg(phy->base, r))  in hdmi_phy_dump()
42 int hdmi_phy_parse_lanes(struct hdmi_phy_data *phy, const u32 *lanes)  in hdmi_phy_parse_lanes()  argument
71 		phy->lane_function[lane] = i / 2;  in hdmi_phy_parse_lanes()
72 		phy->lane_polarity[lane] = pol;  in hdmi_phy_parse_lanes()
78 static void hdmi_phy_configure_lanes(struct hdmi_phy_data *phy)  in hdmi_phy_configure_lanes()  argument
113 		lane_cfg |= phy->lane_function[i] << ((3 - i) * 4);  in hdmi_phy_configure_lanes()
115 	pol_val |= phy->lane_polarity[0] << 0;  in hdmi_phy_configure_lanes()
116 	pol_val |= phy->lane_polarity[1] << 3;  in hdmi_phy_configure_lanes()
117 	pol_val |= phy->lane_polarity[2] << 2;  in hdmi_phy_configure_lanes()
118 	pol_val |= phy->lane_polarity[3] << 1;  in hdmi_phy_configure_lanes()
129 	REG_FLD_MOD(phy->base, HDMI_TXPHY_PAD_CFG_CTRL, lane_cfg_val, 26, 22);  in hdmi_phy_configure_lanes()
130 	REG_FLD_MOD(phy->base, HDMI_TXPHY_PAD_CFG_CTRL, pol_val, 30, 27);  in hdmi_phy_configure_lanes()
133 int hdmi_phy_configure(struct hdmi_phy_data *phy, unsigned long hfbitclk,  in hdmi_phy_configure()  argument
142 	hdmi_read_reg(phy->base, HDMI_TXPHY_TX_CTRL);  in hdmi_phy_configure()
149 		REG_FLD_MOD(phy->base, HDMI_TXPHY_BIST_CONTROL, 1, 11, 11);  in hdmi_phy_configure()
166 	REG_FLD_MOD(phy->base, HDMI_TXPHY_TX_CTRL, freqout, 31, 30);  in hdmi_phy_configure()
169 	hdmi_write_reg(phy->base, HDMI_TXPHY_DIGITAL_CTRL, 0xF0000000);  in hdmi_phy_configure()
173 		REG_FLD_MOD(phy->base, HDMI_TXPHY_POWER_CTRL, 0xB, 3, 0);  in hdmi_phy_configure()
175 	hdmi_phy_configure_lanes(phy);  in hdmi_phy_configure()
225 int hdmi_phy_init(struct platform_device *pdev, struct hdmi_phy_data *phy)  in hdmi_phy_init()  argument
240 	phy->base = devm_ioremap_resource(&pdev->dev, res);  in hdmi_phy_init()
241 	if (IS_ERR(phy->base)) {  in hdmi_phy_init()
243 		return PTR_ERR(phy->base);  in hdmi_phy_init()