59 	FLD_GET(dispc_read_reg(idx), start, end)
62 	dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end))
253 static inline u32 dispc_read_reg(const u16 idx)  in dispc_read_reg()  function
280 	dispc.ctx[DISPC_##reg / sizeof(u32)] = dispc_read_reg(DISPC_##reg)
945 	val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));  in dispc_ovl_set_channel_out()
1003 	val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));  in dispc_ovl_get_channel_out()
1106 	val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));  in dispc_ovl_set_vid_color_conv()
1169 		v = dispc_read_reg(DISPC_GLOBAL_BUFFER);  in dispc_init_fifos()
1552 	l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));  in dispc_ovl_set_scaling_common()
2734 	l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));  in dispc_wb_setup()
2917 	l = dispc_read_reg(DISPC_CONTROL);  in dispc_mgr_set_io_pad_mode()
3167 	l = dispc_read_reg(DISPC_DIVISORo(channel));  in dispc_mgr_get_lcd_divisor()
3211 		l = dispc_read_reg(DISPC_DIVISORo(channel));  in dispc_mgr_lclk_rate()
3252 		l = dispc_read_reg(DISPC_DIVISORo(channel));  in dispc_mgr_pclk_rate()
3338 		l = dispc_read_reg(DISPC_DIVISOR);  in dispc_dump_clocks()
3372 #define DUMPREG(r) seq_printf(s, "%-50s %08x\n", #r, dispc_read_reg(r))  in dispc_dump_regs()
3407 	dispc_read_reg(DISPC_REG(i, r)))  in dispc_dump_regs()
3482 	dispc_read_reg(DISPC_REG(plane, name, i)))  in dispc_dump_regs()
3622 	return dispc_read_reg(DISPC_IRQSTATUS);  in dispc_read_irqstatus()
3634 	return dispc_read_reg(DISPC_IRQENABLE);  in dispc_read_irqenable()
3640 	u32 old_mask = dispc_read_reg(DISPC_IRQENABLE);  in dispc_write_irqenable()
3665 		l = dispc_read_reg(DISPC_DIVISOR);  in _omap_dispc_initial_config()
3941 	rev = dispc_read_reg(DISPC_REVISION);  in omap_dispchw_probe()