Lines Matching refs:par
60 void NVWriteCrtc(struct nvidia_par *par, u8 index, u8 value) in NVWriteCrtc() argument
62 VGA_WR08(par->PCIO, par->IOBase + 0x04, index); in NVWriteCrtc()
63 VGA_WR08(par->PCIO, par->IOBase + 0x05, value); in NVWriteCrtc()
65 u8 NVReadCrtc(struct nvidia_par *par, u8 index) in NVReadCrtc() argument
67 VGA_WR08(par->PCIO, par->IOBase + 0x04, index); in NVReadCrtc()
68 return (VGA_RD08(par->PCIO, par->IOBase + 0x05)); in NVReadCrtc()
70 void NVWriteGr(struct nvidia_par *par, u8 index, u8 value) in NVWriteGr() argument
72 VGA_WR08(par->PVIO, VGA_GFX_I, index); in NVWriteGr()
73 VGA_WR08(par->PVIO, VGA_GFX_D, value); in NVWriteGr()
75 u8 NVReadGr(struct nvidia_par *par, u8 index) in NVReadGr() argument
77 VGA_WR08(par->PVIO, VGA_GFX_I, index); in NVReadGr()
78 return (VGA_RD08(par->PVIO, VGA_GFX_D)); in NVReadGr()
80 void NVWriteSeq(struct nvidia_par *par, u8 index, u8 value) in NVWriteSeq() argument
82 VGA_WR08(par->PVIO, VGA_SEQ_I, index); in NVWriteSeq()
83 VGA_WR08(par->PVIO, VGA_SEQ_D, value); in NVWriteSeq()
85 u8 NVReadSeq(struct nvidia_par *par, u8 index) in NVReadSeq() argument
87 VGA_WR08(par->PVIO, VGA_SEQ_I, index); in NVReadSeq()
88 return (VGA_RD08(par->PVIO, VGA_SEQ_D)); in NVReadSeq()
90 void NVWriteAttr(struct nvidia_par *par, u8 index, u8 value) in NVWriteAttr() argument
94 tmp = VGA_RD08(par->PCIO, par->IOBase + 0x0a); in NVWriteAttr()
95 if (par->paletteEnabled) in NVWriteAttr()
99 VGA_WR08(par->PCIO, VGA_ATT_IW, index); in NVWriteAttr()
100 VGA_WR08(par->PCIO, VGA_ATT_W, value); in NVWriteAttr()
102 u8 NVReadAttr(struct nvidia_par *par, u8 index) in NVReadAttr() argument
106 tmp = VGA_RD08(par->PCIO, par->IOBase + 0x0a); in NVReadAttr()
107 if (par->paletteEnabled) in NVReadAttr()
111 VGA_WR08(par->PCIO, VGA_ATT_IW, index); in NVReadAttr()
112 return (VGA_RD08(par->PCIO, VGA_ATT_R)); in NVReadAttr()
114 void NVWriteMiscOut(struct nvidia_par *par, u8 value) in NVWriteMiscOut() argument
116 VGA_WR08(par->PVIO, VGA_MIS_W, value); in NVWriteMiscOut()
118 u8 NVReadMiscOut(struct nvidia_par *par) in NVReadMiscOut() argument
120 return (VGA_RD08(par->PVIO, VGA_MIS_R)); in NVReadMiscOut()
123 void NVEnablePalette(struct nvidia_par *par)
127 tmp = VGA_RD08(par->PCIO, par->IOBase + 0x0a);
128 VGA_WR08(par->PCIO, VGA_ATT_IW, 0x00);
129 par->paletteEnabled = 1;
131 void NVDisablePalette(struct nvidia_par *par)
135 tmp = VGA_RD08(par->PCIO, par->IOBase + 0x0a);
136 VGA_WR08(par->PCIO, VGA_ATT_IW, 0x20);
137 par->paletteEnabled = 0;
140 void NVWriteDacMask(struct nvidia_par *par, u8 value) in NVWriteDacMask() argument
142 VGA_WR08(par->PDIO, VGA_PEL_MSK, value); in NVWriteDacMask()
145 u8 NVReadDacMask(struct nvidia_par *par)
147 return (VGA_RD08(par->PDIO, VGA_PEL_MSK));
150 void NVWriteDacReadAddr(struct nvidia_par *par, u8 value) in NVWriteDacReadAddr() argument
152 VGA_WR08(par->PDIO, VGA_PEL_IR, value); in NVWriteDacReadAddr()
154 void NVWriteDacWriteAddr(struct nvidia_par *par, u8 value) in NVWriteDacWriteAddr() argument
156 VGA_WR08(par->PDIO, VGA_PEL_IW, value); in NVWriteDacWriteAddr()
158 void NVWriteDacData(struct nvidia_par *par, u8 value) in NVWriteDacData() argument
160 VGA_WR08(par->PDIO, VGA_PEL_D, value); in NVWriteDacData()
162 u8 NVReadDacData(struct nvidia_par *par) in NVReadDacData() argument
164 return (VGA_RD08(par->PDIO, VGA_PEL_D)); in NVReadDacData()
167 static int NVIsConnected(struct nvidia_par *par, int output) in NVIsConnected() argument
169 volatile u32 __iomem *PRAMDAC = par->PRAMDAC0; in NVIsConnected()
187 NV_WR32(par->PRAMDAC0, 0x0610, 0x94050140); in NVIsConnected()
188 NV_WR32(par->PRAMDAC0, 0x0608, NV_RD32(par->PRAMDAC0, 0x0608) | in NVIsConnected()
201 NV_WR32(par->PRAMDAC0, 0x0608, dac0_reg608); in NVIsConnected()
209 static void NVSelectHeadRegisters(struct nvidia_par *par, int head) in NVSelectHeadRegisters() argument
212 par->PCIO = par->PCIO0 + 0x2000; in NVSelectHeadRegisters()
213 par->PCRTC = par->PCRTC0 + 0x800; in NVSelectHeadRegisters()
214 par->PRAMDAC = par->PRAMDAC0 + 0x800; in NVSelectHeadRegisters()
215 par->PDIO = par->PDIO0 + 0x2000; in NVSelectHeadRegisters()
217 par->PCIO = par->PCIO0; in NVSelectHeadRegisters()
218 par->PCRTC = par->PCRTC0; in NVSelectHeadRegisters()
219 par->PRAMDAC = par->PRAMDAC0; in NVSelectHeadRegisters()
220 par->PDIO = par->PDIO0; in NVSelectHeadRegisters()
224 static void nv4GetConfig(struct nvidia_par *par) in nv4GetConfig() argument
226 if (NV_RD32(par->PFB, 0x0000) & 0x00000100) { in nv4GetConfig()
227 par->RamAmountKBytes = in nv4GetConfig()
228 ((NV_RD32(par->PFB, 0x0000) >> 12) & 0x0F) * 1024 * 2 + in nv4GetConfig()
231 switch (NV_RD32(par->PFB, 0x0000) & 0x00000003) { in nv4GetConfig()
233 par->RamAmountKBytes = 1024 * 32; in nv4GetConfig()
236 par->RamAmountKBytes = 1024 * 4; in nv4GetConfig()
239 par->RamAmountKBytes = 1024 * 8; in nv4GetConfig()
243 par->RamAmountKBytes = 1024 * 16; in nv4GetConfig()
247 par->CrystalFreqKHz = (NV_RD32(par->PEXTDEV, 0x0000) & 0x00000040) ? in nv4GetConfig()
249 par->CURSOR = &par->PRAMIN[0x1E00]; in nv4GetConfig()
250 par->MinVClockFreqKHz = 12000; in nv4GetConfig()
251 par->MaxVClockFreqKHz = 350000; in nv4GetConfig()
254 static void nv10GetConfig(struct nvidia_par *par) in nv10GetConfig() argument
257 u32 implementation = par->Chipset & 0x0ff0; in nv10GetConfig()
261 if (!(NV_RD32(par->PMC, 0x0004) & 0x01000001)) { in nv10GetConfig()
262 NV_WR32(par->PMC, 0x0004, 0x01000001); in nv10GetConfig()
268 if ((par->Chipset & 0xffff) == 0x01a0) { in nv10GetConfig()
272 par->RamAmountKBytes = (((amt >> 6) & 31) + 1) * 1024; in nv10GetConfig()
273 } else if ((par->Chipset & 0xffff) == 0x01f0) { in nv10GetConfig()
277 par->RamAmountKBytes = (((amt >> 4) & 127) + 1) * 1024; in nv10GetConfig()
279 par->RamAmountKBytes = in nv10GetConfig()
280 (NV_RD32(par->PFB, 0x020C) & 0xFFF00000) >> 10; in nv10GetConfig()
284 par->CrystalFreqKHz = (NV_RD32(par->PEXTDEV, 0x0000) & (1 << 6)) ? in nv10GetConfig()
287 if (par->twoHeads && (implementation != 0x0110)) { in nv10GetConfig()
288 if (NV_RD32(par->PEXTDEV, 0x0000) & (1 << 22)) in nv10GetConfig()
289 par->CrystalFreqKHz = 27000; in nv10GetConfig()
292 par->CURSOR = NULL; /* can't set this here */ in nv10GetConfig()
293 par->MinVClockFreqKHz = 12000; in nv10GetConfig()
294 par->MaxVClockFreqKHz = par->twoStagePLL ? 400000 : 350000; in nv10GetConfig()
299 struct nvidia_par *par = info->par; in NVCommonSetup() local
301 u16 implementation = par->Chipset & 0x0ff0; in NVCommonSetup()
321 par->PRAMIN = par->REGS + (0x00710000 / 4); in NVCommonSetup()
322 par->PCRTC0 = par->REGS + (0x00600000 / 4); in NVCommonSetup()
323 par->PRAMDAC0 = par->REGS + (0x00680000 / 4); in NVCommonSetup()
324 par->PFB = par->REGS + (0x00100000 / 4); in NVCommonSetup()
325 par->PFIFO = par->REGS + (0x00002000 / 4); in NVCommonSetup()
326 par->PGRAPH = par->REGS + (0x00400000 / 4); in NVCommonSetup()
327 par->PEXTDEV = par->REGS + (0x00101000 / 4); in NVCommonSetup()
328 par->PTIMER = par->REGS + (0x00009000 / 4); in NVCommonSetup()
329 par->PMC = par->REGS + (0x00000000 / 4); in NVCommonSetup()
330 par->FIFO = par->REGS + (0x00800000 / 4); in NVCommonSetup()
333 par->PCIO0 = (u8 __iomem *) par->REGS + 0x00601000; in NVCommonSetup()
334 par->PDIO0 = (u8 __iomem *) par->REGS + 0x00681000; in NVCommonSetup()
335 par->PVIO = (u8 __iomem *) par->REGS + 0x000C0000; in NVCommonSetup()
337 par->twoHeads = (par->Architecture >= NV_ARCH_10) && in NVCommonSetup()
342 par->fpScaler = (par->FpScale && par->twoHeads && in NVCommonSetup()
345 par->twoStagePLL = (implementation == 0x0310) || in NVCommonSetup()
346 (implementation == 0x0340) || (par->Architecture >= NV_ARCH_40); in NVCommonSetup()
348 par->WaitVSyncPossible = (par->Architecture >= NV_ARCH_10) && in NVCommonSetup()
351 par->BlendingPossible = ((par->Chipset & 0xffff) != 0x0020); in NVCommonSetup()
354 switch (par->Chipset & 0xffff) { in NVCommonSetup()
409 if (par->Architecture == NV_ARCH_04) in NVCommonSetup()
410 nv4GetConfig(par); in NVCommonSetup()
412 nv10GetConfig(par); in NVCommonSetup()
414 NVSelectHeadRegisters(par, 0); in NVCommonSetup()
416 NVLockUnlock(par, 0); in NVCommonSetup()
418 par->IOBase = (NVReadMiscOut(par) & 0x01) ? 0x3d0 : 0x3b0; in NVCommonSetup()
420 par->Television = 0; in NVCommonSetup()
422 nvidia_create_i2c_busses(par); in NVCommonSetup()
423 if (!par->twoHeads) { in NVCommonSetup()
424 par->CRTCnumber = 0; in NVCommonSetup()
434 if ((par->Chipset & 0x0fff) <= 0x0020) in NVCommonSetup()
437 VGA_WR08(par->PCIO, 0x03D4, 0x28); in NVCommonSetup()
438 if (VGA_RD08(par->PCIO, 0x03D5) & 0x80) { in NVCommonSetup()
439 VGA_WR08(par->PCIO, 0x03D4, 0x33); in NVCommonSetup()
440 if (!(VGA_RD08(par->PCIO, 0x03D5) & 0x01)) in NVCommonSetup()
451 if (par->FlatPanel == -1) { in NVCommonSetup()
452 par->FlatPanel = FlatPanel; in NVCommonSetup()
453 par->Television = Television; in NVCommonSetup()
456 "specified\n", par->FlatPanel ? "DFP" : "CRT"); in NVCommonSetup()
467 if (NV_RD32(par->PRAMDAC0, 0x0000052C) & 0x100) in NVCommonSetup()
471 if (NV_RD32(par->PRAMDAC0, 0x0000252C) & 0x100) in NVCommonSetup()
475 analog_on_A = NVIsConnected(par, 0); in NVCommonSetup()
476 analog_on_B = NVIsConnected(par, 1); in NVCommonSetup()
484 VGA_WR08(par->PCIO, 0x03D4, 0x44); in NVCommonSetup()
485 cr44 = VGA_RD08(par->PCIO, 0x03D5); in NVCommonSetup()
487 VGA_WR08(par->PCIO, 0x03D5, 3); in NVCommonSetup()
488 NVSelectHeadRegisters(par, 1); in NVCommonSetup()
489 NVLockUnlock(par, 0); in NVCommonSetup()
491 VGA_WR08(par->PCIO, 0x03D4, 0x28); in NVCommonSetup()
492 slaved_on_B = VGA_RD08(par->PCIO, 0x03D5) & 0x80; in NVCommonSetup()
494 VGA_WR08(par->PCIO, 0x03D4, 0x33); in NVCommonSetup()
495 tvB = !(VGA_RD08(par->PCIO, 0x03D5) & 0x01); in NVCommonSetup()
498 VGA_WR08(par->PCIO, 0x03D4, 0x44); in NVCommonSetup()
499 VGA_WR08(par->PCIO, 0x03D5, 0); in NVCommonSetup()
500 NVSelectHeadRegisters(par, 0); in NVCommonSetup()
501 NVLockUnlock(par, 0); in NVCommonSetup()
503 VGA_WR08(par->PCIO, 0x03D4, 0x28); in NVCommonSetup()
504 slaved_on_A = VGA_RD08(par->PCIO, 0x03D5) & 0x80; in NVCommonSetup()
506 VGA_WR08(par->PCIO, 0x03D4, 0x33); in NVCommonSetup()
507 tvA = !(VGA_RD08(par->PCIO, 0x03D5) & 0x01); in NVCommonSetup()
510 oldhead = NV_RD32(par->PCRTC0, 0x00000860); in NVCommonSetup()
511 NV_WR32(par->PCRTC0, 0x00000860, oldhead | 0x00000010); in NVCommonSetup()
567 if (par->FlatPanel == -1) { in NVCommonSetup()
569 par->FlatPanel = FlatPanel; in NVCommonSetup()
570 par->Television = Television; in NVCommonSetup()
577 par->FlatPanel = 1; in NVCommonSetup()
580 par->FlatPanel = 0; in NVCommonSetup()
585 "specified\n", par->FlatPanel ? "DFP" : "CRT"); in NVCommonSetup()
588 if (par->CRTCnumber == -1) { in NVCommonSetup()
590 par->CRTCnumber = CRTCnumber; in NVCommonSetup()
594 if (par->FlatPanel) in NVCommonSetup()
595 par->CRTCnumber = 1; in NVCommonSetup()
597 par->CRTCnumber = 0; in NVCommonSetup()
599 par->CRTCnumber); in NVCommonSetup()
603 "specified\n", par->CRTCnumber); in NVCommonSetup()
608 par->FlatPanel) || in NVCommonSetup()
610 !par->FlatPanel)) { in NVCommonSetup()
623 !par->FlatPanel) || in NVCommonSetup()
625 par->FlatPanel)) { in NVCommonSetup()
633 cr44 = par->CRTCnumber * 0x3; in NVCommonSetup()
635 NV_WR32(par->PCRTC0, 0x00000860, oldhead); in NVCommonSetup()
637 VGA_WR08(par->PCIO, 0x03D4, 0x44); in NVCommonSetup()
638 VGA_WR08(par->PCIO, 0x03D5, cr44); in NVCommonSetup()
639 NVSelectHeadRegisters(par, par->CRTCnumber); in NVCommonSetup()
643 par->FlatPanel ? (par->Television ? "TV" : "DFP") : "CRT", in NVCommonSetup()
644 par->CRTCnumber); in NVCommonSetup()
646 if (par->FlatPanel && !par->Television) { in NVCommonSetup()
647 par->fpWidth = NV_RD32(par->PRAMDAC, 0x0820) + 1; in NVCommonSetup()
648 par->fpHeight = NV_RD32(par->PRAMDAC, 0x0800) + 1; in NVCommonSetup()
649 par->fpSyncs = NV_RD32(par->PRAMDAC, 0x0848) & 0x30000033; in NVCommonSetup()
651 printk("nvidiafb: Panel size is %i x %i\n", par->fpWidth, par->fpHeight); in NVCommonSetup()
657 if (!par->FlatPanel || !par->twoHeads) in NVCommonSetup()
658 par->FPDither = 0; in NVCommonSetup()
660 par->LVDS = 0; in NVCommonSetup()
661 if (par->FlatPanel && par->twoHeads) { in NVCommonSetup()
662 NV_WR32(par->PRAMDAC0, 0x08B0, 0x00010004); in NVCommonSetup()
663 if (NV_RD32(par->PRAMDAC0, 0x08b4) & 1) in NVCommonSetup()
664 par->LVDS = 1; in NVCommonSetup()
665 printk("nvidiafb: Panel is %s\n", par->LVDS ? "LVDS" : "TMDS"); in NVCommonSetup()