Lines Matching refs:pllSPLL_CNTL
661 rinfo->save_regs[74] = INPLL(pllSPLL_CNTL); in radeon_pm_save_regs()
1465 tmp = INPLL(pllSPLL_CNTL); in radeon_pm_all_ppls_off()
1466 OUTPLL(pllSPLL_CNTL, tmp | 0x3); in radeon_pm_all_ppls_off()
1480 tmp = INPLL(pllSPLL_CNTL); in radeon_pm_start_mclk_sclk()
1481 OUTREG8(CLOCK_CNTL_INDEX, pllSPLL_CNTL + PLL_WR_EN); in radeon_pm_start_mclk_sclk()
1492 tmp = INPLL(pllSPLL_CNTL); in radeon_pm_start_mclk_sclk()
1493 OUTPLL(pllSPLL_CNTL, tmp & ~1); in radeon_pm_start_mclk_sclk()
1494 (void)INPLL(pllSPLL_CNTL); in radeon_pm_start_mclk_sclk()
1499 tmp = INPLL(pllSPLL_CNTL); in radeon_pm_start_mclk_sclk()
1500 OUTPLL(pllSPLL_CNTL, tmp & ~0x2); in radeon_pm_start_mclk_sclk()
1501 (void)INPLL(pllSPLL_CNTL); in radeon_pm_start_mclk_sclk()
1655 OUTREG8(CLOCK_CNTL_INDEX, pllSPLL_CNTL + PLL_WR_EN); in radeon_pm_restore_pixel_pll()
1860 OUTPLL(pllSPLL_CNTL, rinfo->save_regs[74] | 0x03); in radeon_reinitialize_M10()
2092 OUTPLL(pllSPLL_CNTL, rinfo->save_regs[74] | 0x03); in radeon_reinitialize_M9P()