508 	switch((INPLL(PPLL_REF_DIV) & 0x30000) >> 16) {  in radeon_probe_pll_params()
515 		n = ((INPLL(M_SPLL_REF_FB_DIV) >> 16) & 0xff);  in radeon_probe_pll_params()
516 		m = (INPLL(M_SPLL_REF_FB_DIV) & 0xff);  in radeon_probe_pll_params()
521 		n = ((INPLL(M_SPLL_REF_FB_DIV) >> 8) & 0xff);  in radeon_probe_pll_params()
522 		m = (INPLL(M_SPLL_REF_FB_DIV) & 0xff);  in radeon_probe_pll_params()
531 	n = (INPLL(PPLL_DIV_0 + ppll_div_sel) & 0x7ff);  in radeon_probe_pll_params()
532 	m = (INPLL(PPLL_REF_DIV) & 0x3ff);  in radeon_probe_pll_params()
537 	switch ((INPLL(PPLL_DIV_0 + ppll_div_sel) >> 16) & 0x7) {  in radeon_probe_pll_params()
573 	tmp = INPLL(M_SPLL_REF_FB_DIV);  in radeon_probe_pll_params()
574 	ref_div = INPLL(PPLL_REF_DIV) & 0x3ff;  in radeon_probe_pll_params()
653 	rinfo->pll.ref_div = INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK;  in radeon_get_pllinfo()
1012 			tmp_pix_clks = INPLL(PIXCLKS_CNTL);  in radeon_screen_blank()
1132 			vclk_cntl = INPLL(VCLK_ECP_CNTL);  in radeonfb_setcolreg()
1162 			vclk_cntl = INPLL(VCLK_ECP_CNTL);  in radeonfb_setcmap()
1228 	save->vclk_ecp_cntl = INPLL(VCLK_ECP_CNTL);  in radeon_save_state()
1233 	save->ppll_div_3 = INPLL(PPLL_DIV_3);  in radeon_save_state()
1234 	save->ppll_ref_div = INPLL(PPLL_REF_DIV);  in radeon_save_state()
1253 		if ((mode->ppll_ref_div == (INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK)) &&  in radeon_write_pll_regs()
1254 		    (mode->ppll_div_3 == (INPLL(PPLL_DIV_3) &  in radeon_write_pll_regs()
1307 	while (INPLL(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R)  in radeon_write_pll_regs()
1316 	for (i = 0; (i < 10000 && INPLL(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R); i++)  in radeon_write_pll_regs()