Lines Matching refs:par
22 u8 aty_ld_pll_ct(int offset, const struct atyfb_par *par) in aty_ld_pll_ct() argument
27 aty_st_8(CLOCK_CNTL_ADDR, (offset << 2) & PLL_ADDR, par); in aty_ld_pll_ct()
29 res = aty_ld_8(CLOCK_CNTL_DATA, par); in aty_ld_pll_ct()
33 static void aty_st_pll_ct(int offset, u8 val, const struct atyfb_par *par) in aty_st_pll_ct() argument
36 aty_st_8(CLOCK_CNTL_ADDR, ((offset << 2) & PLL_ADDR) | PLL_WR_EN, par); in aty_st_pll_ct()
38 aty_st_8(CLOCK_CNTL_DATA, val & PLL_DATA, par); in aty_st_pll_ct()
39 aty_st_8(CLOCK_CNTL_ADDR, ((offset << 2) & PLL_ADDR) & ~PLL_WR_EN, par); in aty_st_pll_ct()
142 struct atyfb_par *par = (struct atyfb_par *) info->par; in aty_dsp_gt() local
144 multiplier = multiplier * par->lcd_width; in aty_dsp_gt()
147 ras_multiplier = ras_multiplier * par->lcd_width; in aty_dsp_gt()
211 struct atyfb_par *par = (struct atyfb_par *) info->par; in aty_valid_pll_ct() local
215 q = par->ref_clk_per * pll->pll_ref_div * 4 / vclk_per; in aty_valid_pll_ct()
228 (par->ref_clk_per * pll->pll_ref_div); in aty_valid_pll_ct()
236 if (par->pll_limits.ecp_max) { in aty_valid_pll_ct()
240 while (ecp > par->pll_limits.ecp_max && ecp_div < 2) { in aty_valid_pll_ct()
252 struct atyfb_par *par = (struct atyfb_par *) info->par; in aty_var_to_pll_ct() local
265 struct atyfb_par *par = (struct atyfb_par *) info->par; in aty_pll_to_var_ct() local
267 …ret = par->ref_clk_per * pll->ct.pll_ref_div * pll->ct.vclk_post_div_real / pll->ct.vclk_fb_div / … in aty_pll_to_var_ct()
270 ret *= par->lcd_width; in aty_pll_to_var_ct()
282 struct atyfb_par *par = (struct atyfb_par *) info->par; in aty_set_pll_ct() local
295 par->clk_wr_offset, pll->ct.vclk_fb_div, in aty_set_pll_ct()
299 if (par->lcd_table != 0) { in aty_set_pll_ct()
301 lcd_gen_cntrl = aty_ld_lcd(LCD_GEN_CNTL, par); in aty_set_pll_ct()
302 aty_st_lcd(LCD_GEN_CNTL, lcd_gen_cntrl & ~LCD_ON, par); in aty_set_pll_ct()
305 aty_st_8(CLOCK_CNTL, par->clk_wr_offset | CLOCK_STROBE, par); in aty_set_pll_ct()
308 crtc_gen_cntl = aty_ld_le32(CRTC_GEN_CNTL, par); in aty_set_pll_ct()
310 aty_st_le32(CRTC_GEN_CNTL, crtc_gen_cntl | CRTC_EXT_DISP_EN, par); in aty_set_pll_ct()
313 aty_st_pll_ct(PLL_VCLK_CNTL, pll->ct.pll_vclk_cntl, par); in aty_set_pll_ct()
316 tmp2 = par->clk_wr_offset << 1; in aty_set_pll_ct()
317 tmp = aty_ld_pll_ct(VCLK_POST_DIV, par); in aty_set_pll_ct()
320 aty_st_pll_ct(VCLK_POST_DIV, tmp, par); in aty_set_pll_ct()
323 tmp = aty_ld_pll_ct(PLL_EXT_CNTL, par); in aty_set_pll_ct()
324 tmp &= ~(0x10U << par->clk_wr_offset); in aty_set_pll_ct()
327 aty_st_pll_ct(PLL_EXT_CNTL, tmp, par); in aty_set_pll_ct()
330 tmp = VCLK0_FB_DIV + par->clk_wr_offset; in aty_set_pll_ct()
331 aty_st_pll_ct(tmp, (pll->ct.vclk_fb_div & 0xFFU), par); in aty_set_pll_ct()
333 …y_st_pll_ct(PLL_GEN_CNTL, (pll->ct.pll_gen_cntl & (~(PLL_OVERRIDE | PLL_MCLK_RST))) | OSC_EN, par); in aty_set_pll_ct()
336 aty_st_pll_ct(PLL_VCLK_CNTL, pll->ct.pll_vclk_cntl & ~(PLL_VCLK_RST), par); in aty_set_pll_ct()
339 aty_st_pll_ct(PLL_GEN_CNTL, pll->ct.pll_gen_cntl, par); in aty_set_pll_ct()
340 aty_st_pll_ct(PLL_VCLK_CNTL, pll->ct.pll_vclk_cntl, par); in aty_set_pll_ct()
345 aty_st_le32(CRTC_GEN_CNTL, crtc_gen_cntl, par); in aty_set_pll_ct()
352 else if (par->ram_type >= SDRAM) in aty_set_pll_ct()
356 aty_st_pll_ct(DLL_CNTL, dll_cntl, par); in aty_set_pll_ct()
357 aty_st_pll_ct(VFC_CNTL, 0x1b, par); in aty_set_pll_ct()
358 aty_st_le32(DSP_CONFIG, pll->ct.dsp_config, par); in aty_set_pll_ct()
359 aty_st_le32(DSP_ON_OFF, pll->ct.dsp_on_off, par); in aty_set_pll_ct()
362 aty_st_pll_ct(DLL_CNTL, dll_cntl, par); in aty_set_pll_ct()
364 aty_st_pll_ct(DLL_CNTL, dll_cntl | 0x40, par); in aty_set_pll_ct()
366 aty_st_pll_ct(DLL_CNTL, dll_cntl & ~0x40, par); in aty_set_pll_ct()
369 if (par->lcd_table != 0) { in aty_set_pll_ct()
371 aty_st_lcd(LCD_GEN_CNTL, lcd_gen_cntrl, par); in aty_set_pll_ct()
378 struct atyfb_par *par = (struct atyfb_par *) info->par; in aty_get_pll_ct() local
381 clock = aty_ld_8(CLOCK_CNTL, par) & 0x03U; in aty_get_pll_ct()
383 pll->ct.vclk_post_div = (aty_ld_pll_ct(VCLK_POST_DIV, par) >> tmp) & 0x03U; in aty_get_pll_ct()
385 pll->ct.pll_ext_cntl = aty_ld_pll_ct(PLL_EXT_CNTL, par) & 0x0FU; in aty_get_pll_ct()
386 pll->ct.vclk_fb_div = aty_ld_pll_ct(VCLK0_FB_DIV + clock, par) & 0xFFU; in aty_get_pll_ct()
387 pll->ct.pll_ref_div = aty_ld_pll_ct(PLL_REF_DIV, par); in aty_get_pll_ct()
388 pll->ct.mclk_fb_div = aty_ld_pll_ct(MCLK_FB_DIV, par); in aty_get_pll_ct()
390 pll->ct.pll_gen_cntl = aty_ld_pll_ct(PLL_GEN_CNTL, par); in aty_get_pll_ct()
391 pll->ct.pll_vclk_cntl = aty_ld_pll_ct(PLL_VCLK_CNTL, par); in aty_get_pll_ct()
394 pll->ct.dsp_config = aty_ld_le32(DSP_CONFIG, par); in aty_get_pll_ct()
395 pll->ct.dsp_on_off = aty_ld_le32(DSP_ON_OFF, par); in aty_get_pll_ct()
401 struct atyfb_par *par = (struct atyfb_par *) info->par; in aty_init_pll_ct() local
408 pll->ct.pll_ext_cntl = aty_ld_pll_ct(PLL_EXT_CNTL, par); in aty_init_pll_ct()
435 memcntl = aty_ld_le32(MEM_CNTL, par); in aty_init_pll_ct()
449 switch (par->ram_type) { in aty_init_pll_ct()
489 dsp_config = aty_ld_le32(DSP_CONFIG, par); in aty_init_pll_ct()
490 dsp_on_off = aty_ld_le32(DSP_ON_OFF, par); in aty_init_pll_ct()
491 vga_dsp_config = aty_ld_le32(VGA_DSP_CONFIG, par); in aty_init_pll_ct()
492 vga_dsp_on_off = aty_ld_le32(VGA_DSP_ON_OFF, par); in aty_init_pll_ct()
511 if (par->mclk_per == 0) { in aty_init_pll_ct()
513 pll->ct.pll_ref_div = aty_ld_pll_ct(PLL_REF_DIV, par); in aty_init_pll_ct()
514 pll_ext_cntl = aty_ld_pll_ct(PLL_EXT_CNTL, par); in aty_init_pll_ct()
516 mclk_fb_div = aty_ld_pll_ct(MCLK_FB_DIV, par); in aty_init_pll_ct()
523 pll->ct.pll_ref_div = par->pll_per * 2 * 255 / par->ref_clk_per; in aty_init_pll_ct()
526 q = par->ref_clk_per * pll->ct.pll_ref_div * 8 / in aty_init_pll_ct()
527 (pll->ct.mclk_fb_mult * par->xclk_per); in aty_init_pll_ct()
550 (par->ref_clk_per * pll->ct.pll_ref_div); in aty_init_pll_ct()
555 if (M64_HAS(SDRAM_MAGIC_PLL) && (par->ram_type >= SDRAM)) in aty_init_pll_ct()
568 if (par->mclk_per == par->xclk_per) { in aty_init_pll_ct()
577 q = par->ref_clk_per * pll->ct.pll_ref_div * 4 / par->mclk_per; in aty_init_pll_ct()
591 (par->ref_clk_per * pll->ct.pll_ref_div); in aty_init_pll_ct()
598 pll->ct.ext_vpll_cntl = aty_ld_pll_ct(EXT_VPLL_CNTL, par); in aty_init_pll_ct()
607 struct atyfb_par *par = info->par; in aty_resume_pll_ct() local
609 if (par->mclk_per != par->xclk_per) { in aty_resume_pll_ct()
617 aty_st_pll_ct(SCLK_FB_DIV, pll->ct.sclk_fb_div, par); in aty_resume_pll_ct()
618 aty_st_pll_ct(SPLL_CNTL2, pll->ct.spll_cntl2, par); in aty_resume_pll_ct()
626 aty_st_pll_ct(PLL_REF_DIV, pll->ct.pll_ref_div, par); in aty_resume_pll_ct()
627 aty_st_pll_ct(PLL_GEN_CNTL, pll->ct.pll_gen_cntl, par); in aty_resume_pll_ct()
628 aty_st_pll_ct(MCLK_FB_DIV, pll->ct.mclk_fb_div, par); in aty_resume_pll_ct()
629 aty_st_pll_ct(PLL_EXT_CNTL, pll->ct.pll_ext_cntl, par); in aty_resume_pll_ct()
630 aty_st_pll_ct(EXT_VPLL_CNTL, pll->ct.ext_vpll_cntl, par); in aty_resume_pll_ct()