123 #define	NO_VIRT		0  macro
594 	p_setb(perm, PCI_CACHE_LINE_SIZE, NO_VIRT, (u8)ALL_WRITE);  in init_pci_cap_basic_perm()
595 	p_setb(perm, PCI_LATENCY_TIMER, NO_VIRT, (u8)ALL_WRITE);  in init_pci_cap_basic_perm()
596 	p_setb(perm, PCI_BIST, NO_VIRT, (u8)ALL_WRITE);  in init_pci_cap_basic_perm()
670 	p_setd(perm, PCI_PM_CTRL, NO_VIRT, ~PCI_PM_CTRL_STATE_MASK);  in init_pci_cap_pm_perm()
683 	p_setw(perm, PCI_X_CMD, NO_VIRT, (u16)ALL_WRITE);  in init_pci_cap_pcix_perm()
684 	p_setd(perm, PCI_X_ECC_CSR, NO_VIRT, ALL_WRITE);  in init_pci_cap_pcix_perm()
702 	p_setw(perm, PCI_EXP_DEVCTL, NO_VIRT, ~PCI_EXP_DEVCTL_PHANTOM);  in init_pci_cap_exp_perm()
703 	p_setw(perm, PCI_EXP_DEVCTL2, NO_VIRT, ~PCI_EXP_DEVCTL2_ARI);  in init_pci_cap_exp_perm()
714 	p_setb(perm, PCI_AF_CTRL, NO_VIRT, PCI_AF_CTRL_FLR);  in init_pci_cap_af_perm()
751 	p_setd(perm, PCI_ERR_UNCOR_STATUS, NO_VIRT, mask);  in init_pci_ext_cap_err_perm()
752 	p_setd(perm, PCI_ERR_UNCOR_MASK, NO_VIRT, mask);  in init_pci_ext_cap_err_perm()
753 	p_setd(perm, PCI_ERR_UNCOR_SEVER, NO_VIRT, mask);  in init_pci_ext_cap_err_perm()
763 	p_setd(perm, PCI_ERR_COR_STATUS, NO_VIRT, mask);  in init_pci_ext_cap_err_perm()
764 	p_setd(perm, PCI_ERR_COR_MASK, NO_VIRT, mask);  in init_pci_ext_cap_err_perm()
768 	p_setd(perm, PCI_ERR_CAP, NO_VIRT, mask);  in init_pci_ext_cap_err_perm()
781 	p_setb(perm, PCI_PWR_DATA, NO_VIRT, (u8)ALL_WRITE);  in init_pci_ext_cap_pwr_perm()
930 			p_setd(perm, PCI_MSI_MASK_64, NO_VIRT, ALL_WRITE);  in init_pci_cap_msi_perm()
931 			p_setd(perm, PCI_MSI_PENDING_64, NO_VIRT, ALL_WRITE);  in init_pci_cap_msi_perm()
936 			p_setd(perm, PCI_MSI_MASK_32, NO_VIRT, ALL_WRITE);  in init_pci_cap_msi_perm()
937 			p_setd(perm, PCI_MSI_PENDING_32, NO_VIRT, ALL_WRITE);  in init_pci_cap_msi_perm()