53 	rev = musb_readl(tbase, TUSB_DMA_CTRL_REV) & 0xff;  in tusb_get_revision()
55 		die_id = TUSB_DIDR1_HI_CHIP_REV(musb_readl(tbase,  in tusb_get_revision()
73 		TUSB_REV_MAJOR(musb_readl(tbase, TUSB_PRCM_REV)),  in tusb_print_revision()
74 		TUSB_REV_MINOR(musb_readl(tbase, TUSB_PRCM_REV)),  in tusb_print_revision()
76 		TUSB_REV_MAJOR(musb_readl(tbase, TUSB_INT_CTRL_REV)),  in tusb_print_revision()
77 		TUSB_REV_MINOR(musb_readl(tbase, TUSB_INT_CTRL_REV)),  in tusb_print_revision()
79 		TUSB_REV_MAJOR(musb_readl(tbase, TUSB_GPIO_REV)),  in tusb_print_revision()
80 		TUSB_REV_MINOR(musb_readl(tbase, TUSB_GPIO_REV)),  in tusb_print_revision()
82 		TUSB_REV_MAJOR(musb_readl(tbase, TUSB_DMA_CTRL_REV)),  in tusb_print_revision()
83 		TUSB_REV_MINOR(musb_readl(tbase, TUSB_DMA_CTRL_REV)),  in tusb_print_revision()
85 		TUSB_DIDR1_HI_CHIP_REV(musb_readl(tbase, TUSB_DIDR1_HI)),  in tusb_print_revision()
104 		phy_otg_ctrl = musb_readl(tbase, TUSB_PHY_OTG_CTRL);  in tusb_wbus_quirk()
105 		phy_otg_ena = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE);  in tusb_wbus_quirk()
113 			musb_readl(tbase, TUSB_PHY_OTG_CTRL),  in tusb_wbus_quirk()
114 			musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE));  in tusb_wbus_quirk()
115 	} else if (musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE)  in tusb_wbus_quirk()
122 			musb_readl(tbase, TUSB_PHY_OTG_CTRL),  in tusb_wbus_quirk()
123 			musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE));  in tusb_wbus_quirk()
209 			val = musb_readl(fifo, 0);  in tusb_fifo_read_unaligned()
217 		val = musb_readl(fifo, 0);  in tusb_fifo_read_unaligned()
304 					val = musb_readl(fifo, 0);  in tusb_read_fifo()
346 	reg = musb_readl(tbase, TUSB_PRCM_MNGMT);  in tusb_draw_power()
369 	reg = musb_readl(tbase, TUSB_PRCM_CONF);  in tusb_set_clock_source()
410 	reg = musb_readl(tbase, TUSB_PRCM_MNGMT);  in tusb_allow_idle()
434 	otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);  in tusb_musb_vbus_status()
435 	prcm_mngmt = musb_readl(tbase, TUSB_PRCM_MNGMT);  in tusb_musb_vbus_status()
445 		otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);  in tusb_musb_vbus_status()
566 	prcm = musb_readl(tbase, TUSB_PRCM_MNGMT);  in tusb_musb_set_vbus()
567 	conf = musb_readl(tbase, TUSB_DEV_CONF);  in tusb_musb_set_vbus()
584 		otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);  in tusb_musb_set_vbus()
620 		musb_readl(tbase, TUSB_DEV_OTG_STAT),  in tusb_musb_set_vbus()
636 	otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);  in tusb_musb_set_mode()
637 	phy_otg_ctrl = musb_readl(tbase, TUSB_PHY_OTG_CTRL);  in tusb_musb_set_mode()
638 	phy_otg_ena = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE);  in tusb_musb_set_mode()
639 	dev_conf = musb_readl(tbase, TUSB_DEV_CONF);  in tusb_musb_set_mode()
671 	otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);  in tusb_musb_set_mode()
683 	u32		otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);  in tusb_otg_ints()
832 	int_mask = musb_readl(tbase, TUSB_INT_MASK);  in tusb_musb_interrupt()
835 	int_src = musb_readl(tbase, TUSB_INT_SRC) & ~TUSB_INT_SRC_RESERVED_BITS;  in tusb_musb_interrupt()
854 			reg = musb_readl(tbase, TUSB_SCRATCH_PAD);  in tusb_musb_interrupt()
863 		reg = musb_readl(tbase, TUSB_PRCM_WAKEUP_SOURCE);  in tusb_musb_interrupt()
888 		u32	dma_src = musb_readl(tbase, TUSB_DMA_INT_SRC);  in tusb_musb_interrupt()
889 		u32	real_dma_src = musb_readl(tbase, TUSB_DMA_INT_MASK);  in tusb_musb_interrupt()
909 		u32	musb_src = musb_readl(tbase, TUSB_USBIP_INT_SRC);  in tusb_musb_interrupt()
970 	if (!(musb_readl(tbase, TUSB_DEV_OTG_STAT)  in tusb_musb_enable()
1053 	if (musb_readl(tbase, TUSB_PROD_TEST_RESET) !=  in tusb_musb_start()
1086 	reg = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE);  in tusb_musb_start()
1090 	reg = musb_readl(tbase, TUSB_PHY_OTG_CTRL);  in tusb_musb_start()