947 	u16			rx_csr, tx_csr;  in musb_bulk_nak_timeout()  local
964 		tx_csr = musb_readw(epio, MUSB_TXCSR);  in musb_bulk_nak_timeout()
965 		tx_csr |= MUSB_TXCSR_H_WZC_BITS;  in musb_bulk_nak_timeout()
966 		tx_csr &= ~MUSB_TXCSR_H_NAKTIMEOUT;  in musb_bulk_nak_timeout()
967 		musb_writew(epio, MUSB_TXCSR, tx_csr);  in musb_bulk_nak_timeout()
1229 	u16			tx_csr;  in musb_host_tx()  local
1242 	tx_csr = musb_readw(epio, MUSB_TXCSR);  in musb_host_tx()
1246 		dev_dbg(musb->controller, "extra TX%d ready, csr %04x\n", epnum, tx_csr);  in musb_host_tx()
1252 	dev_dbg(musb->controller, "OUT/TX%d end, csr %04x%s\n", epnum, tx_csr,  in musb_host_tx()
1256 	if (tx_csr & MUSB_TXCSR_H_RXSTALL) {  in musb_host_tx()
1263 	} else if (tx_csr & MUSB_TXCSR_H_ERROR) {  in musb_host_tx()
1269 	} else if (tx_csr & MUSB_TXCSR_H_NAKTIMEOUT) {  in musb_host_tx()
1305 		tx_csr &= ~(MUSB_TXCSR_AUTOSET  in musb_host_tx()
1313 		musb_writew(epio, MUSB_TXCSR, tx_csr);  in musb_host_tx()
1315 		musb_writew(epio, MUSB_TXCSR, tx_csr);  in musb_host_tx()
1323 		dev_dbg(musb->controller, "extra TX%d ready, csr %04x\n", epnum, tx_csr);  in musb_host_tx()
1336 		if (tx_csr & MUSB_TXCSR_DMAMODE) {  in musb_host_tx()
1353 			tx_csr &= musb_readw(epio, MUSB_TXCSR);  in musb_host_tx()
1354 			if (tx_csr & MUSB_TXCSR_TXPKTRDY) {  in musb_host_tx()
1355 				tx_csr &= ~(MUSB_TXCSR_DMAENAB |  in musb_host_tx()
1358 					    tx_csr | MUSB_TXCSR_H_WZC_BITS);  in musb_host_tx()
1360 			tx_csr &= ~(MUSB_TXCSR_DMAMODE |  in musb_host_tx()
1363 				    tx_csr | MUSB_TXCSR_H_WZC_BITS);  in musb_host_tx()
1371 			tx_csr = musb_readw(epio, MUSB_TXCSR);  in musb_host_tx()
1381 		if (tx_csr & (MUSB_TXCSR_FIFONOTEMPTY | MUSB_TXCSR_TXPKTRDY)) {  in musb_host_tx()
1383 			    "CSR %04x\n", tx_csr);  in musb_host_tx()
1448 	} else	if (tx_csr & MUSB_TXCSR_DMAENAB) {  in musb_host_tx()