Lines Matching refs:MUSB_CSR0
533 musb_writew(regs, MUSB_CSR0, csr); in ep0_rxstate()
553 dev_dbg(musb->controller, "odd; csr0 %04x\n", musb_readw(regs, MUSB_CSR0)); in ep0_txstate()
590 musb_writew(regs, MUSB_CSR0, csr); in ep0_txstate()
638 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_P_SVDRXPKTRDY); in musb_read_setup()
639 while ((musb_readw(regs, MUSB_CSR0) in musb_read_setup()
675 csr = musb_readw(regs, MUSB_CSR0); in musb_g_ep0_irq()
691 musb_writew(regs, MUSB_CSR0, in musb_g_ep0_irq()
695 csr = musb_readw(regs, MUSB_CSR0); in musb_g_ep0_irq()
700 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_P_SVDSETUPEND); in musb_g_ep0_irq()
714 csr = musb_readw(regs, MUSB_CSR0); in musb_g_ep0_irq()
888 musb_writew(regs, MUSB_CSR0, in musb_g_ep0_irq()
905 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_P_SENDSTALL); in musb_g_ep0_irq()
989 musb_writew(regs, MUSB_CSR0, in musb_g_ep0_queue()
1000 musb_writew(regs, MUSB_CSR0, musb->ackpend); in musb_g_ep0_queue()
1051 csr = musb_readw(regs, MUSB_CSR0); in musb_g_ep0_halt()
1061 musb_writew(regs, MUSB_CSR0, csr); in musb_g_ep0_halt()