30 #define UDC_EPCTL_ADDR		0x00	/* Endpoint control */  macro
639 		pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_F);  in pch_udc_ep_set_stall()
640 		pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_S);  in pch_udc_ep_set_stall()
642 		pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_S);  in pch_udc_ep_set_stall()
653 	pch_udc_ep_bit_clr(ep, UDC_EPCTL_ADDR, UDC_EPCTL_S);  in pch_udc_ep_clear_stall()
655 	pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_CNAK);  in pch_udc_ep_clear_stall()
667 				UDC_EPCTL_ET_MASK), UDC_EPCTL_ADDR);  in pch_udc_ep_set_trfr_type()
728 	pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_P);  in pch_udc_ep_set_pd()
737 	pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_RRDY);  in pch_udc_ep_set_rrdy()
746 	pch_udc_ep_bit_clr(ep, UDC_EPCTL_ADDR, UDC_EPCTL_RRDY);  in pch_udc_ep_clear_rrdy()
894 	return pch_udc_ep_readl(ep, UDC_EPCTL_ADDR);  in pch_udc_read_ep_control()
904 	return pch_udc_ep_writel(ep, 0, UDC_EPCTL_ADDR);  in pch_udc_clear_ep_control()
935 	pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_SNAK);  in pch_udc_ep_set_nak()
948 	if (!(pch_udc_ep_readl(ep, UDC_EPCTL_ADDR) & UDC_EPCTL_NAK))  in pch_udc_ep_clear_nak()
961 		pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_CNAK);  in pch_udc_ep_clear_nak()
979 		pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_F);  in pch_udc_ep_fifo_flush()
1028 		pch_udc_ep_writel(ep, UDC_EPCTL_F, UDC_EPCTL_ADDR);  in pch_udc_ep_disable()
1030 		pch_udc_ep_writel(ep, UDC_EPCTL_SNAK, UDC_EPCTL_ADDR);  in pch_udc_ep_disable()
1034 		pch_udc_ep_writel(ep, UDC_EPCTL_SNAK, UDC_EPCTL_ADDR);  in pch_udc_ep_disable()