1845 	u32 scratch;  in defect7374_enable_data_eps_zero()  local
1849 	scratch = get_idx_reg(dev->regs, SCRATCH);  in defect7374_enable_data_eps_zero()
1851 	WARN_ON((scratch & (0xf << DEFECT7374_FSM_FIELD))  in defect7374_enable_data_eps_zero()
1854 	scratch &= ~(0xf << DEFECT7374_FSM_FIELD);  in defect7374_enable_data_eps_zero()
1909 	scratch |= DEFECT7374_FSM_WAITING_FOR_CONTROL_READ;  in defect7374_enable_data_eps_zero()
1910 	set_idx_reg(dev->regs, SCRATCH, scratch);  in defect7374_enable_data_eps_zero()
2582 	u32 scratch, fsmvalue;  in defect7374_workaround()  local
2586 	scratch = get_idx_reg(dev->regs, SCRATCH);  in defect7374_workaround()
2587 	fsmvalue = scratch & (0xf << DEFECT7374_FSM_FIELD);  in defect7374_workaround()
2588 	scratch &= ~(0xf << DEFECT7374_FSM_FIELD);  in defect7374_workaround()
2602 		scratch |= DEFECT7374_FSM_NON_SS_CONTROL_READ;  in defect7374_workaround()
2616 			scratch |= DEFECT7374_FSM_SS_CONTROL_READ;  in defect7374_workaround()
2649 	set_idx_reg(dev->regs, SCRATCH, scratch);  in defect7374_workaround()
2880 	u32			num, scratch;  in handle_stat0_irqs()  local
2977 			scratch = BIT(DATA_PACKET_TRANSMITTED_INTERRUPT) |  in handle_stat0_irqs()
2982 			scratch = BIT(DATA_PACKET_RECEIVED_INTERRUPT) |  in handle_stat0_irqs()
2985 		writel(scratch, &dev->epregs[0].ep_irqenb);  in handle_stat0_irqs()
3102 	scratch = stat & 0x7f;  in handle_stat0_irqs()
3104 	for (num = 0; scratch; num++) {  in handle_stat0_irqs()
3109 		if ((scratch & t) == 0)  in handle_stat0_irqs()
3111 		scratch ^= t;  in handle_stat0_irqs()
3135 	u32			tmp, num, mask, scratch;  in handle_stat1_irqs()  local
3233 	scratch = stat & DMA_INTERRUPTS;  in handle_stat1_irqs()
3235 	scratch >>= 9;  in handle_stat1_irqs()
3236 	for (num = 0; scratch; num++) {  in handle_stat1_irqs()
3240 		if ((tmp & scratch) == 0)  in handle_stat1_irqs()
3242 		scratch ^= tmp;  in handle_stat1_irqs()