57 #define gr_write32(x, v) (iowrite32be((v), (x)))  macro
412 	gr_write32(&ep->regs->dmaaddr, req->curr_desc->paddr);  in gr_start_dma()
416 	gr_write32(&ep->regs->dmactrl, dmactrl | GR_DMACTRL_DA);  in gr_start_dma()
447 	gr_write32(&ep->regs->dmactrl, dmactrl | GR_DMACTRL_AD);  in gr_abort_dma()
693 	gr_write32(&ep->regs->epctrl, 0);  in gr_ep_reset()
694 	gr_write32(&ep->regs->dmactrl, 0);  in gr_ep_reset()
712 	gr_write32(&dev->epo[0].regs->epctrl, epctrl | GR_EPCTRL_CS);  in gr_control_stall()
714 	gr_write32(&dev->epi[0].regs->epctrl, epctrl | GR_EPCTRL_CS);  in gr_control_stall()
752 		gr_write32(&ep->regs->epctrl, epctrl | GR_EPCTRL_EH);  in gr_ep_halt_wedge()
757 		gr_write32(&ep->regs->epctrl, epctrl & ~GR_EPCTRL_EH);  in gr_ep_halt_wedge()
785 	gr_write32(&dev->regs->control, 0);  in gr_disable_interrupts_and_pullup()
825 	gr_write32(&dev->regs->control, control);  in gr_ep0_testmode_complete()
898 	gr_write32(&dev->regs->control, control);  in gr_set_address()
1199 	gr_write32(&dev->regs->control, control);  in gr_vbus_connected()
1209 	gr_write32(&dev->regs->control, GR_CONTROL_VI);  in gr_enable_vbus_detect()
1325 		gr_write32(&ep->regs->dmactrl, ep_dmactrl | GR_DMACTRL_DA);  in gr_handle_out_ep()
1361 		gr_write32(&dev->regs->status, GR_STATUS_UR);  in gr_handle_state_changes()
1608 	gr_write32(&ep->regs->epctrl, epctrl);  in gr_ep_enable()
1610 	gr_write32(&ep->regs->dmactrl, GR_DMACTRL_IE | GR_DMACTRL_AI);  in gr_ep_enable()
1840 	gr_write32(&ep->regs->epctrl, epctrl);  in gr_fifo_flush()
1888 	gr_write32(&dev->regs->control,  in gr_wakeup()
1912 	gr_write32(&dev->regs->control, control);  in gr_pullup()
2076 	gr_write32(&dev->epo[0].regs->epctrl, epctrl_val);  in gr_udc_init()
2077 	gr_write32(&dev->epi[0].regs->epctrl, epctrl_val | GR_EPCTRL_PI);  in gr_udc_init()
2078 	gr_write32(&dev->epo[0].regs->dmactrl, dmactrl_val);  in gr_udc_init()
2079 	gr_write32(&dev->epi[0].regs->dmactrl, dmactrl_val);  in gr_udc_init()