196 				dev->int_enable &= ~(INT_MSTWREND  in ep_reset()
199 				dev->int_enable &= ~INT_MSTRDEND;  in ep_reset()
200 			dev->int_enable &= ~INT_EPxDATASET (ep->num);  in ep_reset()
202 			dev->int_enable &= ~INT_EP0;  in ep_reset()
203 		writel(dev->int_enable, &regs->int_enable);  in ep_reset()
204 		readl(&regs->int_enable);  in ep_reset()
502 	dev->int_enable |= INT_EPxDATASET (epnum);  in pio_irq_enable()
503 	writel(dev->int_enable, &regs->int_enable);  in pio_irq_enable()
511 	dev->int_enable &= ~INT_EPxDATASET (epnum);  in pio_irq_disable()
512 	writel(dev->int_enable, &regs->int_enable);  in pio_irq_disable()
559 		ep->dev->int_enable |= INT_MSTRDEND;  in start_dma()
578 		ep->dev->int_enable |= INT_MSTWREND|INT_MSTWRTMOUT;  in start_dma()
582 	writel(ep->dev->int_enable, &regs->int_enable);  in start_dma()
597 			dev->int_enable &= ~INT_MSTRDEND;  in dma_advance()
599 			dev->int_enable &= ~(INT_MSTWREND|INT_MSTWRTMOUT);  in dma_advance()
600 		writel(dev->int_enable, &regs->int_enable);  in dma_advance()
780 			&& !(dev->int_enable & INT_EPxDATASET (ep->num)))  in goku_queue()
1129 	dump_intmask(m, "int_enable", readl(&regs->int_enable));  in udc_proc_read()
1272 	writel(0, &regs->int_enable);  in udc_reset()
1273 	readl(&regs->int_enable);  in udc_reset()
1274 	dev->int_enable = 0;  in udc_reset()
1281 	readl(&regs->int_enable);  in udc_reset()
1312 	dev->int_enable = INT_DEVWIDE | INT_EP0;  in ep0_start()
1313 	writel(dev->int_enable, &dev->regs->int_enable);  in ep0_start()
1314 	readl(&regs->int_enable);  in ep0_start()
1326 		dev->int_enable = INT_PWRDETECT;  in udc_enable()
1327 		writel(dev->int_enable, &dev->regs->int_enable);  in udc_enable()
1519 	stat = readl(&regs->int_status) & dev->int_enable;  in goku_irq()
1545 				dev->int_enable = INT_DEVWIDE;  in goku_irq()
1546 				writel(dev->int_enable, &dev->regs->int_enable);  in goku_irq()
1662 	(void)readl(&regs->int_enable);  in goku_irq()
1666 				readl(&regs->int_status), dev->int_enable);  in goku_irq()