96 	u32			csr;  in proc_ep_show()  local
103 	csr = __raw_readl(ep->creg);  in proc_ep_show()
117 		csr,  in proc_ep_show()
118 		(csr & 0x07ff0000) >> 16,  in proc_ep_show()
119 		(csr & (1 << 15)) ? "enabled" : "disabled",  in proc_ep_show()
120 		(csr & (1 << 11)) ? "DATA1" : "DATA0",  in proc_ep_show()
121 		types[(csr & 0x700) >> 8],  in proc_ep_show()
124 		(!(csr & 0x700))  in proc_ep_show()
125 			? ((csr & (1 << 7)) ? " IN" : " OUT")  in proc_ep_show()
127 		(csr & (1 << 6)) ? " rxdatabk1" : "",  in proc_ep_show()
128 		(csr & (1 << 5)) ? " forcestall" : "",  in proc_ep_show()
129 		(csr & (1 << 4)) ? " txpktrdy" : "",  in proc_ep_show()
131 		(csr & (1 << 3)) ? " stallsent" : "",  in proc_ep_show()
132 		(csr & (1 << 2)) ? " rxsetup" : "",  in proc_ep_show()
133 		(csr & (1 << 1)) ? " rxdatabk0" : "",  in proc_ep_show()
134 		(csr & (1 << 0)) ? " txcomp" : "");  in proc_ep_show()
311 	u32		csr;  in read_fifo()  local
323 	csr = __raw_readl(creg);  in read_fifo()
324 	if ((csr & RX_DATA_READY) == 0)  in read_fifo()
327 	count = (csr & AT91_UDP_RXBYTECNT) >> 16;  in read_fifo()
338 	csr |= CLR_FX;  in read_fifo()
341 			csr &= ~(SET_FX | AT91_UDP_RX_DATA_BK0);  in read_fifo()
344 			csr &= ~(SET_FX | AT91_UDP_RX_DATA_BK1);  in read_fifo()
348 		csr &= ~(SET_FX | AT91_UDP_RX_DATA_BK0);  in read_fifo()
349 	__raw_writel(csr, creg);  in read_fifo()
371 		csr = __raw_readl(creg);  in read_fifo()
385 	u32		csr = __raw_readl(creg);  in write_fifo()  local
402 	if (unlikely(csr & (AT91_UDP_TXCOMP | AT91_UDP_TXPKTRDY))) {  in write_fifo()
403 		if (csr & AT91_UDP_TXCOMP) {  in write_fifo()
404 			csr |= CLR_FX;  in write_fifo()
405 			csr &= ~(SET_FX | AT91_UDP_TXCOMP);  in write_fifo()
406 			__raw_writel(csr, creg);  in write_fifo()
407 			csr = __raw_readl(creg);  in write_fifo()
409 		if (csr & AT91_UDP_TXPKTRDY)  in write_fifo()
438 	csr &= ~SET_FX;  in write_fifo()
439 	csr |= CLR_FX | AT91_UDP_TXPKTRDY;  in write_fifo()
440 	__raw_writel(csr, creg);  in write_fifo()
736 	u32		csr;  in at91_ep_set_halt()  local
746 	csr = __raw_readl(creg);  in at91_ep_set_halt()
753 	if (ep->is_in && (!list_empty(&ep->queue) || (csr >> 16) != 0))  in at91_ep_set_halt()
756 		csr |= CLR_FX;  in at91_ep_set_halt()
757 		csr &= ~SET_FX;  in at91_ep_set_halt()
759 			csr |= AT91_UDP_FORCESTALL;  in at91_ep_set_halt()
764 			csr &= ~AT91_UDP_FORCESTALL;  in at91_ep_set_halt()
766 		__raw_writel(csr, creg);  in at91_ep_set_halt()
1004 	u32			csr = __raw_readl(creg);  in handle_ep()  local
1013 		if (csr & (AT91_UDP_STALLSENT | AT91_UDP_TXCOMP)) {  in handle_ep()
1014 			csr |= CLR_FX;  in handle_ep()
1015 			csr &= ~(SET_FX | AT91_UDP_STALLSENT | AT91_UDP_TXCOMP);  in handle_ep()
1016 			__raw_writel(csr, creg);  in handle_ep()
1022 		if (csr & AT91_UDP_STALLSENT) {  in handle_ep()
1026 			csr |= CLR_FX;  in handle_ep()
1027 			csr &= ~(SET_FX | AT91_UDP_STALLSENT);  in handle_ep()
1028 			__raw_writel(csr, creg);  in handle_ep()
1029 			csr = __raw_readl(creg);  in handle_ep()
1031 		if (req && (csr & RX_DATA_READY))  in handle_ep()
1042 static void handle_setup(struct at91_udc *udc, struct at91_ep *ep, u32 csr)  in handle_setup()  argument
1052 	rxcount = (csr & AT91_UDP_RXBYTECNT) >> 16;  in handle_setup()
1057 			csr |= AT91_UDP_DIR;  in handle_setup()
1060 			csr &= ~AT91_UDP_DIR;  in handle_setup()
1065 		ERR("SETUP len %d, csr %08x\n", rxcount, csr);  in handle_setup()
1068 	csr |= CLR_FX;  in handle_setup()
1069 	csr &= ~(SET_FX | AT91_UDP_RXSETUP);  in handle_setup()
1070 	__raw_writel(csr, creg);  in handle_setup()
1090 	csr = __raw_readl(creg);  in handle_setup()
1091 	csr |= CLR_FX;  in handle_setup()
1092 	csr &= ~SET_FX;  in handle_setup()
1097 		__raw_writel(csr | AT91_UDP_TXPKTRDY, creg);  in handle_setup()
1253 		csr |= AT91_UDP_FORCESTALL;  in handle_setup()
1254 		__raw_writel(csr, creg);  in handle_setup()
1263 	csr |= AT91_UDP_TXPKTRDY;  in handle_setup()
1264 	__raw_writel(csr, creg);  in handle_setup()
1272 	u32			csr = __raw_readl(creg);  in handle_ep0()  local
1275 	if (unlikely(csr & AT91_UDP_STALLSENT)) {  in handle_ep0()
1278 		csr |= CLR_FX;  in handle_ep0()
1279 		csr &= ~(SET_FX | AT91_UDP_STALLSENT | AT91_UDP_FORCESTALL);  in handle_ep0()
1280 		__raw_writel(csr, creg);  in handle_ep0()
1282 		csr = __raw_readl(creg);  in handle_ep0()
1284 	if (csr & AT91_UDP_RXSETUP) {  in handle_ep0()
1287 		handle_setup(udc, ep0, csr);  in handle_ep0()
1297 	if (csr & AT91_UDP_TXCOMP) {  in handle_ep0()
1298 		csr |= CLR_FX;  in handle_ep0()
1299 		csr &= ~(SET_FX | AT91_UDP_TXCOMP);  in handle_ep0()
1316 			__raw_writel(csr, creg);  in handle_ep0()
1340 	else if (csr & AT91_UDP_RX_DATA_BK0) {  in handle_ep0()
1341 		csr |= CLR_FX;  in handle_ep0()
1342 		csr &= ~(SET_FX | AT91_UDP_RX_DATA_BK0);  in handle_ep0()
1350 					csr = __raw_readl(creg);  in handle_ep0()
1351 					csr &= ~SET_FX;  in handle_ep0()
1352 					csr |= CLR_FX | AT91_UDP_TXPKTRDY;  in handle_ep0()
1353 					__raw_writel(csr, creg);  in handle_ep0()
1375 				__raw_writel(csr | AT91_UDP_FORCESTALL, creg);  in handle_ep0()
1382 			__raw_writel(csr, creg);  in handle_ep0()