182 	DBG(dev, "dev control    = %08x\n", readl(&dev->regs->ctl));  in print_regs()
300 	if (readl(&ep->regs->ctl) & AMD_BIT(UDC_EPCTL_NAK)) {  in UDC_QUEUE_CNAK()
340 	tmp = readl(&dev->ep[ep->num].regs->ctl);  in udc_ep_enable()
342 	writel(tmp, &dev->ep[ep->num].regs->ctl);  in udc_ep_enable()
371 		tmp = readl(&ep->regs->ctl);  in udc_ep_enable()
373 		writel(tmp, &ep->regs->ctl);  in udc_ep_enable()
425 		tmp = readl(&ep->regs->ctl);  in udc_ep_enable()
427 		writel(tmp, &ep->regs->ctl);  in udc_ep_enable()
450 	tmp = readl(&ep->regs->ctl);  in ep_init()
452 	writel(tmp, &ep->regs->ctl);  in ep_init()
462 		tmp = readl(&ep->regs->ctl);  in ep_init()
464 		writel(tmp, &ep->regs->ctl);  in ep_init()
471 		tmp = readl(&ep->regs->ctl);  in ep_init()
473 		writel(tmp, &ep->regs->ctl);  in ep_init()
802 				tmp = readl(&ep->regs->ctl);  in prep_dma()
804 				writel(tmp, &ep->regs->ctl);  in prep_dma()
1042 	tmp = readl(&dev->regs->ctl);  in udc_set_rde()
1044 	writel(tmp, &dev->regs->ctl);  in udc_set_rde()
1105 				tmp = readl(&dev->regs->ctl);  in udc_queue()
1107 				writel(tmp, &dev->regs->ctl);  in udc_queue()
1113 				tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->ctl);  in udc_queue()
1115 				writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl);  in udc_queue()
1144 				tmp = readl(&dev->regs->ctl);  in udc_queue()
1146 				writel(tmp, &dev->regs->ctl);  in udc_queue()
1165 				tmp = readl(&ep->regs->ctl);  in udc_queue()
1167 				writel(tmp, &ep->regs->ctl);  in udc_queue()
1276 				tmp = readl(&udc->regs->ctl);  in udc_dequeue()
1278 							&udc->regs->ctl);  in udc_dequeue()
1292 				writel(tmp, &udc->regs->ctl);  in udc_dequeue()
1333 			tmp = readl(&ep->regs->ctl);  in udc_set_halt()
1335 			writel(tmp, &ep->regs->ctl);  in udc_set_halt()
1352 			tmp = readl(&ep->regs->ctl);  in udc_set_halt()
1357 			writel(tmp, &ep->regs->ctl);  in udc_set_halt()
1479 	tmp = readl(&dev->regs->ctl);  in udc_basic_init()
1482 	writel(tmp, &dev->regs->ctl);  in udc_basic_init()
1549 			ep->dma = &dev->regs->ctl;  in udc_setup_endpoints()
1555 				reg = readl(&dev->ep[tmp].regs->ctl);  in udc_setup_endpoints()
1557 				writel(reg, &dev->ep[tmp].regs->ctl);  in udc_setup_endpoints()
1706 			tmp = readl(&udc->regs->ctl);  in udc_timer_function()
1708 			writel(tmp, &udc->regs->ctl);  in udc_timer_function()
1748 		tmp = readl(&ep->regs->ctl);  in udc_handle_halt_state()
1765 			writel(tmp, &ep->regs->ctl);  in udc_handle_halt_state()
1814 	tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->ctl);  in activate_control_endpoints()
1816 	writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl);  in activate_control_endpoints()
1879 		tmp = readl(&dev->regs->ctl);  in activate_control_endpoints()
1887 		writel(tmp, &dev->regs->ctl);  in activate_control_endpoints()
1891 	tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->ctl);  in activate_control_endpoints()
1893 	writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl);  in activate_control_endpoints()
1898 	tmp = readl(&dev->ep[UDC_EP0OUT_IX].regs->ctl);  in activate_control_endpoints()
1900 	writel(tmp, &dev->ep[UDC_EP0OUT_IX].regs->ctl);  in activate_control_endpoints()
1937 	tmp = readl(&dev->regs->ctl);  in amd5536_udc_start()
1939 	writel(tmp, &dev->regs->ctl);  in amd5536_udc_start()
1978 	tmp = readl(&dev->regs->ctl);  in amd5536_udc_stop()
1980 	writel(tmp, &dev->regs->ctl);  in amd5536_udc_stop()
1997 			reg = readl(&dev->ep[tmp].regs->ctl);  in udc_process_cnak_queue()
1999 			writel(reg, &dev->ep[tmp].regs->ctl);  in udc_process_cnak_queue()
2008 		reg = readl(&dev->ep[UDC_EP0OUT_IX].regs->ctl);  in udc_process_cnak_queue()
2010 		writel(reg, &dev->ep[UDC_EP0OUT_IX].regs->ctl);  in udc_process_cnak_queue()
2394 					tmp = readl(&ep->regs->ctl);  in udc_data_in_isr()
2396 					writel(tmp, &ep->regs->ctl);  in udc_data_in_isr()
2458 		tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->ctl);  in udc_control_out_isr()
2460 		writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl);  in udc_control_out_isr()
2540 		tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->ctl);  in udc_control_out_isr()
2546 			writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl);  in udc_control_out_isr()
2553 			writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl);  in udc_control_out_isr()
2560 			tmp = readl(&dev->ep[UDC_EP0OUT_IX].regs->ctl);  in udc_control_out_isr()
2562 			writel(tmp, &dev->ep[UDC_EP0OUT_IX].regs->ctl);  in udc_control_out_isr()
2669 			tmp = readl(&ep->regs->ctl);  in udc_control_in_isr()
2671 			writel(tmp, &ep->regs->ctl);  in udc_control_in_isr()
2690 					readl(&dev->ep[UDC_EP0IN_IX].regs->ctl);  in udc_control_in_isr()
2693 					&dev->ep[UDC_EP0IN_IX].regs->ctl);  in udc_control_in_isr()
2785 			tmp = readl(&ep->regs->ctl);  in udc_dev_isr()
2787 			writel(tmp, &ep->regs->ctl);  in udc_dev_isr()
2844 			tmp = readl(&ep->regs->ctl);  in udc_dev_isr()
2846 			writel(tmp, &ep->regs->ctl);  in udc_dev_isr()
3109 	dev->ep[UDC_EP0IN_IX].dma = &dev->regs->ctl;  in init_dma_pools()
3307 	reg = readl(&dev->regs->ctl);  in udc_probe()
3309 	writel(reg, &dev->regs->ctl);  in udc_probe()
3330 	tmp = readl(&dev->regs->ctl);  in udc_remote_wakeup()
3332 	writel(tmp, &dev->regs->ctl);  in udc_remote_wakeup()
3334 	writel(tmp, &dev->regs->ctl);  in udc_remote_wakeup()