1526 	unsigned char RegValue;  in set_break()  local
1538 	RegValue = read_reg(info, CTL);  in set_break()
1540 		RegValue |= BIT3;  in set_break()
1542 		RegValue &= ~BIT3;  in set_break()
1543 	write_reg(info, CTL, RegValue);  in set_break()
4385   	unsigned char RegValue;  in async_mode()  local
4400 	RegValue = 0x00;  in async_mode()
4402 		RegValue |= BIT1;  in async_mode()
4403 	write_reg(info, MD0, RegValue);  in async_mode()
4414 	RegValue = 0x40;  in async_mode()
4416 	case 7: RegValue |= BIT4 + BIT2; break;  in async_mode()
4417 	case 6: RegValue |= BIT5 + BIT3; break;  in async_mode()
4418 	case 5: RegValue |= BIT5 + BIT4 + BIT3 + BIT2; break;  in async_mode()
4421 		RegValue |= BIT1;  in async_mode()
4423 			RegValue |= BIT0;  in async_mode()
4425 	write_reg(info, MD1, RegValue);  in async_mode()
4434 	RegValue = 0x00;  in async_mode()
4436 		RegValue |= (BIT1 + BIT0);  in async_mode()
4437 	write_reg(info, MD2, RegValue);  in async_mode()
4445 	RegValue=BIT6;  in async_mode()
4446 	write_reg(info, RXS, RegValue);  in async_mode()
4454 	RegValue=BIT6;  in async_mode()
4455 	write_reg(info, TXS, RegValue);  in async_mode()
4499 	RegValue = 0x10;  in async_mode()
4501 		RegValue |= 0x01;  in async_mode()
4502 	write_reg(info, CTL, RegValue);  in async_mode()
4523 	unsigned char RegValue;  in hdlc_mode()  local
4547 	RegValue = 0x81;  in hdlc_mode()
4549 		RegValue |= BIT4;  in hdlc_mode()
4551 		RegValue |= BIT4;  in hdlc_mode()
4553 		RegValue |= BIT2 + BIT1;  in hdlc_mode()
4554 	write_reg(info, MD0, RegValue);  in hdlc_mode()
4565 	RegValue = 0x00;  in hdlc_mode()
4566 	write_reg(info, MD1, RegValue);  in hdlc_mode()
4578 	RegValue = 0x00;  in hdlc_mode()
4580 	case HDLC_ENCODING_NRZI:	  RegValue |= BIT5; break;  in hdlc_mode()
4581 	case HDLC_ENCODING_BIPHASE_MARK:  RegValue |= BIT7 + BIT5; break; /* aka FM1 */  in hdlc_mode()
4582 	case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT7 + BIT6; break; /* aka FM0 */  in hdlc_mode()
4583 	case HDLC_ENCODING_BIPHASE_LEVEL: RegValue |= BIT7; break; 	/* aka Manchester */  in hdlc_mode()
4592 		RegValue |= BIT3;  in hdlc_mode()
4597 		RegValue |= BIT4;  in hdlc_mode()
4599 	write_reg(info, MD2, RegValue);  in hdlc_mode()
4608 	RegValue=0;  in hdlc_mode()
4610 		RegValue |= BIT6;  in hdlc_mode()
4612 		RegValue |= BIT6 + BIT5;  in hdlc_mode()
4613 	write_reg(info, RXS, RegValue);  in hdlc_mode()
4621 	RegValue=0;  in hdlc_mode()
4623 		RegValue |= BIT6;  in hdlc_mode()
4625 		RegValue |= BIT6 + BIT5;  in hdlc_mode()
4626 	write_reg(info, TXS, RegValue);  in hdlc_mode()
4704 	RegValue = 0x10;  in hdlc_mode()
4706 		RegValue |= 0x01;  in hdlc_mode()
4707 	write_reg(info, CTL, RegValue);  in hdlc_mode()
4725 	unsigned char RegValue = 0xff;  in tx_set_idle()  local
4729 	case HDLC_TXIDLE_FLAGS:			RegValue = 0x7e; break;  in tx_set_idle()
4730 	case HDLC_TXIDLE_ALT_ZEROS_ONES:	RegValue = 0xaa; break;  in tx_set_idle()
4731 	case HDLC_TXIDLE_ZEROS:			RegValue = 0x00; break;  in tx_set_idle()
4732 	case HDLC_TXIDLE_ONES:			RegValue = 0xff; break;  in tx_set_idle()
4733 	case HDLC_TXIDLE_ALT_MARK_SPACE:	RegValue = 0xaa; break;  in tx_set_idle()
4734 	case HDLC_TXIDLE_SPACE:			RegValue = 0x00; break;  in tx_set_idle()
4735 	case HDLC_TXIDLE_MARK:			RegValue = 0xff; break;  in tx_set_idle()
4738 	write_reg(info, IDL, RegValue);  in tx_set_idle()
4774 	unsigned char RegValue;  in set_signals()  local
4777 	RegValue = read_reg(info, CTL);  in set_signals()
4779 		RegValue &= ~BIT0;  in set_signals()
4781 		RegValue |= BIT0;  in set_signals()
4782 	write_reg(info, CTL, RegValue);  in set_signals()