Lines Matching refs:DSR
374 #define DSR 0x90 macro
2235 write_reg(info, TXDMA + DSR, 0xc0); /* clear IRQs and disable DMA */ in isr_txeom()
2352 unsigned char status = read_reg(info,RXDMA + DSR) & 0xc0; in isr_rxdmaok()
2355 write_reg(info, RXDMA + DSR, (unsigned char)(status | 1)); in isr_rxdmaok()
2369 unsigned char status = read_reg(info,RXDMA + DSR) & 0x30; in isr_rxdmaerror()
2372 write_reg(info, RXDMA + DSR, (unsigned char)(status | 1)); in isr_rxdmaerror()
2387 write_reg(info, TXDMA + DSR, 0xc0); /* clear IRQs and disable DMA */ in isr_txdmaok()
2405 unsigned char status = read_reg(info,TXDMA + DSR) & 0x30; in isr_txdmaerror()
2408 write_reg(info, TXDMA + DSR, (unsigned char)(status | 1)); in isr_txdmaerror()
2999 write_reg(info, TXDMA + DSR, 0); /* disable DMA channel */ in tx_abort()
4133 write_reg(info, RXDMA + DSR, 0); /* disable Rx DMA */ in rx_stop()
4159 write_reg(info, RXDMA + DSR, 0); /* disable Rx DMA */ in rx_start()
4184 write_reg(info, RXDMA + DSR, 0xf2); /* clear Rx DMA IRQs, enable Rx DMA */ in rx_start()
4234 write_reg(info, TXDMA + DSR, 0); /* disable DMA channel */ in tx_start()
4252 write_reg(info, TXDMA + DSR, 0xf2); /* clear Tx DMA IRQs, enable Tx DMA */ in tx_start()
4278 write_reg(info, TXDMA + DSR, 0); /* disable DMA channel */ in tx_stop()