1460 		outw( (inw(info->io_base + CCAR) & 0x0780) | (RDR+LSBONLY),  in mgsl_isr_receive_data()
4496 	outw( Cmd + info->loopback_bits, info->io_base + CCAR );  in usc_RTCmd()
4521 	outw( Cmd + info->mbre_bit, info->io_base );  in usc_DmaCmd()
4550 	outw( RegAddr + info->mbre_bit, info->io_base );  in usc_OutDmaReg()
4551 	outw( RegValue, info->io_base );  in usc_OutDmaReg()
4579 	outw( RegAddr + info->mbre_bit, info->io_base );  in usc_InDmaReg()
4603 	outw( RegAddr + info->loopback_bits, info->io_base + CCAR );  in usc_OutReg()
4604 	outw( RegValue, info->io_base + CCAR );  in usc_OutReg()
4628 	outw( RegAddr + info->loopback_bits, info->io_base + CCAR );  in usc_InReg()
5063 	outw( 0, info->io_base ); 			/* clear Master Bus Enable (DCAR) */  in usc_set_sdlc_mode()
5066 	outw( BIT8, info->io_base );			/* set Master Bus Enable (DCAR) */  in usc_set_sdlc_mode()
5256 		outw( 0x0300, info->io_base + CCAR );  in usc_enable_loopback()
5263 		outw( 0,info->io_base + CCAR );  in usc_enable_loopback()
5733 			outw( *((u16 *)TwoBytes), info->io_base + DATAREG);  in usc_load_txfifo()
5740 			outw( (inw( info->io_base + CCAR) & 0x0780) | (TDR+LSBONLY),  in usc_load_txfifo()
5745 				outw( info->x_char,info->io_base + CCAR );  in usc_load_txfifo()
5748 				outw( info->xmit_buf[info->xmit_tail++],info->io_base + CCAR );  in usc_load_txfifo()
5827 	outw( 0x000c,info->io_base + SDPIN );  in usc_reset()
5830 	outw( 0,info->io_base );  in usc_reset()
5831 	outw( 0,info->io_base + CCAR );  in usc_reset()
5886 	outw( 0, info->io_base ); 			/* clear Master Bus Enable (DCAR) */  in usc_set_async_mode()
6058 		outw(0x0300, info->io_base + CCAR);  in usc_set_async_mode()
6120 	outw(0,info->io_base + DATAREG);  in usc_loopback_frame()