260 	unsigned int io_base;		/* base I/O address of adapter */  member
1460 		outw( (inw(info->io_base + CCAR) & 0x0780) | (RDR+LSBONLY),  in mgsl_isr_receive_data()
1461 		      info->io_base + CCAR );  in mgsl_isr_receive_data()
1462 		DataByte = inb( info->io_base + CCAR );  in mgsl_isr_receive_data()
3464 			info->device_name, info->io_base, info->irq_level,  in line_info()
3468 			info->device_name, info->io_base,   in line_info()
3540 	u16 Ccar = inw( info->io_base + CCAR );  in line_info()
4068 	if (request_region(info->io_base,info->io_addr_size,"synclink") == NULL) {  in mgsl_claim_resources()
4070 			__FILE__,__LINE__,info->device_name, info->io_base);  in mgsl_claim_resources()
4169 		release_region(info->io_base,info->io_addr_size);  in mgsl_release_resources()
4246 			info->hw_version + 1, info->device_name, info->io_base, info->irq_level,  in mgsl_add_device()
4251 			info->device_name, info->io_base, info->irq_level, info->dma_level,  in mgsl_add_device()
4392 		info->io_base = (unsigned int)io[i];  in mgsl_enum_isa_devices()
4496 	outw( Cmd + info->loopback_bits, info->io_base + CCAR );  in usc_RTCmd()
4500 		inw( info->io_base + CCAR );  in usc_RTCmd()
4521 	outw( Cmd + info->mbre_bit, info->io_base );  in usc_DmaCmd()
4525 		inw( info->io_base );  in usc_DmaCmd()
4550 	outw( RegAddr + info->mbre_bit, info->io_base );  in usc_OutDmaReg()
4551 	outw( RegValue, info->io_base );  in usc_OutDmaReg()
4555 		inw( info->io_base );  in usc_OutDmaReg()
4579 	outw( RegAddr + info->mbre_bit, info->io_base );  in usc_InDmaReg()
4580 	return inw( info->io_base );  in usc_InDmaReg()
4603 	outw( RegAddr + info->loopback_bits, info->io_base + CCAR );  in usc_OutReg()
4604 	outw( RegValue, info->io_base + CCAR );  in usc_OutReg()
4608 		inw( info->io_base + CCAR );  in usc_OutReg()
4628 	outw( RegAddr + info->loopback_bits, info->io_base + CCAR );  in usc_InReg()
4629 	return inw( info->io_base + CCAR );  in usc_InReg()
5063 	outw( 0, info->io_base ); 			/* clear Master Bus Enable (DCAR) */  in usc_set_sdlc_mode()
5066 	outw( BIT8, info->io_base );			/* set Master Bus Enable (DCAR) */  in usc_set_sdlc_mode()
5256 		outw( 0x0300, info->io_base + CCAR );  in usc_enable_loopback()
5263 		outw( 0,info->io_base + CCAR );  in usc_enable_loopback()
5733 			outw( *((u16 *)TwoBytes), info->io_base + DATAREG);  in usc_load_txfifo()
5740 			outw( (inw( info->io_base + CCAR) & 0x0780) | (TDR+LSBONLY),  in usc_load_txfifo()
5741 				info->io_base + CCAR );  in usc_load_txfifo()
5745 				outw( info->x_char,info->io_base + CCAR );  in usc_load_txfifo()
5748 				outw( info->xmit_buf[info->xmit_tail++],info->io_base + CCAR );  in usc_load_txfifo()
5803 		outb( 0,info->io_base + 8 );  in usc_reset()
5827 	outw( 0x000c,info->io_base + SDPIN );  in usc_reset()
5830 	outw( 0,info->io_base );  in usc_reset()
5831 	outw( 0,info->io_base + CCAR );  in usc_reset()
5886 	outw( 0, info->io_base ); 			/* clear Master Bus Enable (DCAR) */  in usc_set_async_mode()
6058 		outw(0x0300, info->io_base + CCAR);  in usc_set_async_mode()
6120 	outw(0,info->io_base + DATAREG);  in usc_loopback_frame()
7370 			__FILE__,__LINE__,info->device_name, (unsigned short)(info->io_base) );  in mgsl_adapter_test()
8027 	dev->base_addr = info->io_base;  in hdlcdev_init()
8085 	info->io_base = pci_resource_start(dev, 2);  in synclink_init_one()