Lines Matching refs:RegValue
4545 static void usc_OutDmaReg( struct mgsl_struct *info, u16 RegAddr, u16 RegValue ) in usc_OutDmaReg() argument
4551 outw( RegValue, info->io_base ); in usc_OutDmaReg()
4601 static void usc_OutReg( struct mgsl_struct *info, u16 RegAddr, u16 RegValue ) in usc_OutReg() argument
4604 outw( RegValue, info->io_base + CCAR ); in usc_OutReg()
4642 u16 RegValue; in usc_set_sdlc_mode() local
4655 RegValue=usc_InReg(info,TMDR); in usc_set_sdlc_mode()
4656 PreSL1660 = (RegValue == IUSC_PRE_SL1660); in usc_set_sdlc_mode()
4672 RegValue = 0x8e06; in usc_set_sdlc_mode()
4693 RegValue = 0x0001; /* Set Receive mode = external sync */ in usc_set_sdlc_mode()
4710 RegValue |= 0x0400; in usc_set_sdlc_mode()
4714 RegValue = 0x0606; in usc_set_sdlc_mode()
4717 RegValue |= BIT14; in usc_set_sdlc_mode()
4719 RegValue |= BIT15; in usc_set_sdlc_mode()
4721 RegValue |= BIT15 | BIT14; in usc_set_sdlc_mode()
4725 RegValue |= BIT13; in usc_set_sdlc_mode()
4730 RegValue |= BIT12; in usc_set_sdlc_mode()
4736 RegValue |= BIT4; in usc_set_sdlc_mode()
4739 usc_OutReg( info, CMR, RegValue ); in usc_set_sdlc_mode()
4740 info->cmr_value = RegValue; in usc_set_sdlc_mode()
4757 RegValue = 0x0500; in usc_set_sdlc_mode()
4760 case HDLC_ENCODING_NRZB: RegValue |= BIT13; break; in usc_set_sdlc_mode()
4761 case HDLC_ENCODING_NRZI_MARK: RegValue |= BIT14; break; in usc_set_sdlc_mode()
4762 case HDLC_ENCODING_NRZI_SPACE: RegValue |= BIT14 | BIT13; break; in usc_set_sdlc_mode()
4763 case HDLC_ENCODING_BIPHASE_MARK: RegValue |= BIT15; break; in usc_set_sdlc_mode()
4764 case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT15 | BIT13; break; in usc_set_sdlc_mode()
4765 case HDLC_ENCODING_BIPHASE_LEVEL: RegValue |= BIT15 | BIT14; break; in usc_set_sdlc_mode()
4766 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: RegValue |= BIT15 | BIT14 | BIT13; break; in usc_set_sdlc_mode()
4770 RegValue |= BIT9; in usc_set_sdlc_mode()
4772 RegValue |= ( BIT12 | BIT10 | BIT9 ); in usc_set_sdlc_mode()
4774 usc_OutReg( info, RMR, RegValue ); in usc_set_sdlc_mode()
4805 RegValue = usc_InReg( info, RICR ) & 0xc0; in usc_set_sdlc_mode()
4808 usc_OutReg( info, RICR, (u16)(0x030a | RegValue) ); in usc_set_sdlc_mode()
4810 usc_OutReg( info, RICR, (u16)(0x140a | RegValue) ); in usc_set_sdlc_mode()
4832 RegValue = 0x0400; in usc_set_sdlc_mode()
4835 case HDLC_ENCODING_NRZB: RegValue |= BIT13; break; in usc_set_sdlc_mode()
4836 case HDLC_ENCODING_NRZI_MARK: RegValue |= BIT14; break; in usc_set_sdlc_mode()
4837 case HDLC_ENCODING_NRZI_SPACE: RegValue |= BIT14 | BIT13; break; in usc_set_sdlc_mode()
4838 case HDLC_ENCODING_BIPHASE_MARK: RegValue |= BIT15; break; in usc_set_sdlc_mode()
4839 case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT15 | BIT13; break; in usc_set_sdlc_mode()
4840 case HDLC_ENCODING_BIPHASE_LEVEL: RegValue |= BIT15 | BIT14; break; in usc_set_sdlc_mode()
4841 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: RegValue |= BIT15 | BIT14 | BIT13; break; in usc_set_sdlc_mode()
4845 RegValue |= BIT9 | BIT8; in usc_set_sdlc_mode()
4847 RegValue |= ( BIT12 | BIT10 | BIT9 | BIT8); in usc_set_sdlc_mode()
4849 usc_OutReg( info, TMR, RegValue ); in usc_set_sdlc_mode()
4916 RegValue = 0x0f40; in usc_set_sdlc_mode()
4919 RegValue |= 0x0003; /* RxCLK from DPLL */ in usc_set_sdlc_mode()
4921 RegValue |= 0x0004; /* RxCLK from BRG0 */ in usc_set_sdlc_mode()
4923 RegValue |= 0x0006; /* RxCLK from TXC Input */ in usc_set_sdlc_mode()
4925 RegValue |= 0x0007; /* RxCLK from Port1 */ in usc_set_sdlc_mode()
4928 RegValue |= 0x0018; /* TxCLK from DPLL */ in usc_set_sdlc_mode()
4930 RegValue |= 0x0020; /* TxCLK from BRG0 */ in usc_set_sdlc_mode()
4932 RegValue |= 0x0038; /* RxCLK from TXC Input */ in usc_set_sdlc_mode()
4934 RegValue |= 0x0030; /* TxCLK from Port0 */ in usc_set_sdlc_mode()
4936 usc_OutReg( info, CMCR, RegValue ); in usc_set_sdlc_mode()
4954 RegValue = 0x0000; in usc_set_sdlc_mode()
4971 RegValue |= BIT10; in usc_set_sdlc_mode()
4975 RegValue |= BIT11; in usc_set_sdlc_mode()
5008 RegValue |= BIT4; /* enable BRG1 */ in usc_set_sdlc_mode()
5014 case HDLC_ENCODING_NRZI_SPACE: RegValue |= BIT8; break; in usc_set_sdlc_mode()
5016 case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT9; break; in usc_set_sdlc_mode()
5018 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: RegValue |= BIT9 | BIT8; break; in usc_set_sdlc_mode()
5022 usc_OutReg( info, HCR, RegValue ); in usc_set_sdlc_mode()
5169 RegValue = 0x8080; in usc_set_sdlc_mode()
5172 case HDLC_PREAMBLE_LENGTH_16BITS: RegValue |= BIT10; break; in usc_set_sdlc_mode()
5173 case HDLC_PREAMBLE_LENGTH_32BITS: RegValue |= BIT11; break; in usc_set_sdlc_mode()
5174 case HDLC_PREAMBLE_LENGTH_64BITS: RegValue |= BIT11 | BIT10; break; in usc_set_sdlc_mode()
5178 case HDLC_PREAMBLE_PATTERN_FLAGS: RegValue |= BIT8 | BIT12; break; in usc_set_sdlc_mode()
5179 case HDLC_PREAMBLE_PATTERN_ONES: RegValue |= BIT8; break; in usc_set_sdlc_mode()
5180 case HDLC_PREAMBLE_PATTERN_10: RegValue |= BIT9; break; in usc_set_sdlc_mode()
5181 case HDLC_PREAMBLE_PATTERN_01: RegValue |= BIT9 | BIT8; break; in usc_set_sdlc_mode()
5184 usc_OutReg( info, CCR, RegValue ); in usc_set_sdlc_mode()
5881 u16 RegValue; in usc_set_async_mode() local
5903 RegValue = 0; in usc_set_async_mode()
5905 RegValue |= BIT14; in usc_set_async_mode()
5906 usc_OutReg( info, CMR, RegValue ); in usc_set_async_mode()
5921 RegValue = 0; in usc_set_async_mode()
5924 RegValue |= BIT4 | BIT3 | BIT2; in usc_set_async_mode()
5927 RegValue |= BIT5; in usc_set_async_mode()
5929 RegValue |= BIT6; in usc_set_async_mode()
5932 usc_OutReg( info, RMR, RegValue ); in usc_set_async_mode()
5978 RegValue = 0; in usc_set_async_mode()
5981 RegValue |= BIT4 | BIT3 | BIT2; in usc_set_async_mode()
5984 RegValue |= BIT5; in usc_set_async_mode()
5986 RegValue |= BIT6; in usc_set_async_mode()
5989 usc_OutReg( info, TMR, RegValue ); in usc_set_async_mode()